Datasheet

Section 12 Event Link Controller
Page 384 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
3 to 0 C0CLS[3:0]* Channel 0 event-
generation
interval select
0000: Clock source φELC/1
0001: Clock source φELC/2
0010: Clock source φELC/4
0011: Clock source φELC/8
0100: Clock source φELC/16
0101: Clock source φELC/32
0110: Clock source φELC/64
0111: Clock source φELC/128
1000: Clock source φELC/256 (initial value)
1001: Clock source φELC/512
1010: Clock source φELC/1024
1011: Clock source φELC/2048
1100: Clock source φELC/4096
1101: Clock source φELC/8192
1110: Clock source φELC/16384
1111: Clock source φELC/32768
R/W
Notes: Be sure to stop the counter (the TMRSTR bit in ELTMCR is 0) before switching an event
generation interval.
* While system operation clock φ has been selected as a clock source (the CLSRS[3:0]
bits in ELTMCR are B'0000), do not set to B'0000 to the C1CLS[3:0] and C0CLS[3:0]
bits.
ELTMSA determines the event-generation interval for channels 0 and 1, and sets the division ratio
for the clock source specified by ELTMCR.