Datasheet

Section 12 Event Link Controller
Page 382 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
12.2.10 Event-Generation Timer Control Register (ELTMCR)
b7
TMRSTR
0
b6
⎯
1
b5
⎯
1
b4
⎯
1
b3
0
b2
0
b1
0
b0
0
H'FF06B8
CLSRS[3:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 TMRSTR Timer count start 0: Counter is stopped.
1: Counter is incremented.
R/W
6 to 4 ⎯ Reserved These bits are read as 1. The write value should
be 1.
⎯
3 to 0 CLSRS[3:0] Clock source (φELC)
select
0000: φ
0001: φ/2
0010: φ/4
0011: φ/8
0100: φ/16
0101: φ/32
0110: φ/64
0111: φ/128
1000: φ/256
1001: φ/512
1010: φ/1024
1011: φ/2048
1100: φ/4096
1101: φ/8192
1110: Reserved (Counter is stopped.)
1111: Reserved (Counter is stopped.)
R/W
Note: Be sure to stop the counter before changing the clock source.
ELTMCR controls the ELTMCNT operation and selects the clock source.