Datasheet

Section 12 Event Link Controller
Page 380 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
12.2.8 Port Buffer Registers 1 and 2 (PDBF1 and PDBF2)
b7
PDBFn7
0
b6
PDBFn6
0
b5
PDBFn5
0
b4
PDBFn4
0
b3
PDBFn3
0
b2
PDBFn2
0
b1
PDBFn1
0
b0
PDBFn0
0
H'FF06AA, H'FF06AB
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 PDBFn7 Port buffer n7 R/W
6 PDBFn6 Port buffer n6 R/W
5 PDBFn5 Port buffer n5 R/W
4 PDBFn4 Port buffer n4 R/W
3 PDBFn3 Port buffer n3 R/W
2 PDBFn2 Port buffer n2 R/W
1 PDBFn1 Port buffer n1 R/W
0 PDBFn0 Port buffer n0
Data is transferred between PDR and PDBF when
an event is input. Write access to the bit specified as
a member of the input port-group by the CPU is
invalid. For details, see section 12.3, Operation.
R/W
[Legend]
n: 1, 2
PDBF is an 8-bit readable/writable register used in combination with PGR. For PDBF operations,
see section 12.3, Operation. The correspondence of PDBF and PDR is shown in table 12.3.
Table 12.3 Registers Related to Port-Groups and Corresponding Port Numbers
Port Group Setting
Register (PGR)
Port Group Control
Register (PGC)
Port Buffer Register
(PDBF) Port Number
PGR1 PGC1 PDBF1 Port 3
PGR2 PGC2 PDBF2 Port 6