Datasheet

Section 12 Event Link Controller
Page 374 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Table 12.2 Correspondence between Event Signal Names and ELSn Bit Values
ELSn7 to ELSn0 Bit Value
(Signal Number)
Name of Event Signal to Set ELSR
00000001 (H'01) Timer RA underflow
00000010 (H'02) Timer RB underflow
00000011 (H'03)*
1
Timer RC overflow
00000100 (H'04)*
1
Timer RC compare-match A
00000101 (H'05)*
1
Timer RC compare-match B
00000110 (H'06)*
1
Timer RC compare-match C
00000111 (H'07)*
1
Timer RC compare-match D
00001000 (H'08) Timer RD_0 channel 0 overflow
00001001 (H'09) Timer RD_0 channel 0 compare-match A
00001010 (H'0A) Timer RD_0 channel 0 compare-match B
00001011 (H'0B) Timer RD_0 channel 0 compare-match C
00001100 (H'0C) Timer RD_0 channel 0 compare-match D
00001101 (H'0D) Timer RD_0 channel 1 overflow
00001110 (H'0E) Timer RD_0 channel 1 underflow
00001111 (H'0F) Timer RD_0 channel 1 compare-match A
00010000 (H'10) Timer RD_0 channel 1 compare-match B
00010001 (H'11) Timer RD_0 channel 1 compare-match C
00010010 (H'12) Timer RD_0 channel 1 compare-match D
00100001 (H'21) Timer RG overflow
00100010 (H'22) Timer RG underflow
00100011 (H'23) Timer RG compare-match A
00100100 (H'24) Timer RG compare-match B
00101001 (H'29) AD conversion end in AD converter unit 1
00101010 (H'2A)*
2
AD conversion end in AD converter unit 2
00101100 (H'2C) Input edge detection on input port-group 1
00101101 (H'2D) Input edge detection on input port-group 2
00101111 (H'2F) Input edge detection on single input port 0
00110000 (H'30) Input edge detection on single input port 1
00110001 (H'31) Input edge detection on single input port 2
00110010 (H'32) Input edge detection on single input port 3
00110111 (H'37) Voltage-drop detection in LVD