Datasheet

Section 12 Event Link Controller
REJ09B0465-0300 Rev. 3.00 Page 371 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
12.2 Register Descriptions
The ELC has the following registers.
• Event link control register (ELCR)
• Event link setting registers 0 to 32 (ELSR0 to ELSR32)
• Event link option setting register A (ELOPA)
• Event link option setting register B (ELOPB)
• Event link option setting register C (ELOPC)
• Port-group setting registers 1 and 2 (PGR1, PGR2)
• Port-group control registers 1 and 2 (PGC1, PGC2)
• Port buffer registers 1 and 2 (PDBF1 and PDBF2)
• Event link port setting registers 0 to 3 (PEL0 to PEL3)
• Event-generation timer control register (ELTMCR)
• Event-generation timer interval setting register A (ELTMSA)
• Event-generation timer interval setting register B (ELTMSB)
• Event-generation timer delay selection register (ELTMDR)
• ELC timer counter (ELTMCNT)
12.2.1 Event Link Control Register (ELCR)
b7
ELCON
0
b6
⎯
1
b5
⎯
1
b4
⎯
1
b3
⎯
1
b2
⎯
1
b1
⎯
1
b0
⎯
1
H'FF06BC
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 ELCON All event link
enable
0: Linkage of all the events are disabled.
1: Linkage of all the events are enabled.
R/W
6 to 0 ⎯ Reserved These bits are read as 1. The write value should be
1.
⎯
ELCR controls the operation of the event link controller (ELC) collectively.