Datasheet

Section 11 Data Transfer Controller (DTC)
REJ09B0465-0300 Rev. 3.00 Page 359 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
DTC vector
address
Register information
CHNE=1
Register information
CHNE=0
Start address of
register information
Source
Destination
Source
Destination
Figure 11.9 Operation of Chain Transfer
11.5.5 Interrupt Sources
An interrupt request is issued to the CPU when the DTC ends the specified number of data
transfers, or when the DTC ends a data transfer for which the DISEL bit was set to 1. In the case
of interrupt activation, the interrupt set as the activation source is generated. These interrupts to
the CPU are subject to CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended or the specified number of transfers has
ended, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated after data transfer
ends. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.