Datasheet

Section 11 Data Transfer Controller (DTC)
REJ09B0465-0300 Rev. 3.00 Page 355 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Table 11.4 Chain Transfer Conditions
1st Transfer 2nd Transfer
CHNE CHNS DISEL CR CHNE CHNS DISEL CR DTC Transfer
0 ⎯ 0 Except 0 ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer
0 ⎯ 0 0 ⎯ ⎯ ⎯ ⎯
0 ⎯ 1 ⎯ ⎯ ⎯ ⎯ ⎯
Ends at 1st transfer
Interrupt request to CPU
1 0 ⎯ ⎯ 0 ⎯ 0 Except 0 Ends at 2nd transfer
0 ⎯ 0 0
0 ⎯ 1 ⎯
Ends at 2nd transfer
Interrupt request to CPU
1 1 0 Except 0 ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer
1 1 ⎯ 0 0 ⎯ 0 Except 0 Ends at 2nd transfer
0 ⎯ 0 0
0 ⎯ 1 ⎯
Ends at 2nd transfer
Interrupt request to CPU
1 1 1 Except 0 ⎯ ⎯ ⎯ ⎯ Ends at 1st transfer
Interrupt request to CPU
11.5.1 Normal Mode
In normal mode, one operation transfers one byte or one word of data. Table 11.5 lists the register
function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number
of transfers has ended, a CPU interrupt can be requested.
Table 11.5 Register Function in Normal Mode
Name Abbreviation Function
DTC source address register SAR Designates transfer source address
DTC destination address register DAR Designates transfer destination address
DTC transfer count register A CRA Designates transfer count
DTC transfer count register B CRB Not used