Datasheet

Section 11 Data Transfer Controller (DTC)
REJ09B0465-0300 Rev. 3.00 Page 353 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Notes: 1. Vector address indicates the lower 11 bits of vector address when VOFR = H'0000.
2. Supported only in the H8S/20223 and H8S/20235 Groups and reserved in other
products.
3. Supported only in the H8S/20103 and H8S/20115 Groups and reserved in other
products.
4. Not supported in the H8S/20103 and H8S/20115 Groups, and reserved in these groups.
5. DTCE bits with no corresponding interrupt are reserved. The write value should always
be 0.
11.5 Operation
The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information in the on-chip RAM and transfers data. After the data transfer, it writes updated
register information back to the on-chip RAM. Pre-storage of register information in the on-chip
RAM makes it possible to transfer data over any required number of channels. There are three
transfer modes: normal mode, repeat mode, and block transfer mode. Setting the CHNE bit to 1
allows a number of transfers with a single activation (chain transfer). Setting the CHNS bit to 1
enables chain transfer only when the transfer counter value is 0.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed according to the register information.
Figure 11.5 shows a flowchart of DTC operation, and table 11.4 summarizes the chain transfer
conditions (for performing the first and second transfers).