Datasheet

Section 11 Data Transfer Controller (DTC)
Page 348 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
11.4 Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM. Register information should be located at the
address that is multiple of four. Locating the register information in address space is shown in
figure 11.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the
start address of the register information. In the case of chain transfer, register information should
be located in consecutive areas as shown in figure 11.3 and the register information start address
should be located at the corresponding vector address to the activation source. Figure 11.4 shows
correspondences between the DTC vector address and register information. The DTC reads the
start address of the register information from the vector address set for each activation source, and
then reads the register information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if VOFR and DTVECR are H'0000 and H'18 respectively, the
vector address is H'0430.
The configuration of the vector address is a 2-byte unit. These two bytes specify the lower bits of
the start address. Whenever the DTC is used, set the VOFR to H'0000 (its default value).