Datasheet

Section 11 Data Transfer Controller (DTC)
REJ09B0465-0300 Rev. 3.00 Page 345 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
11.2.8 DTC Vector Register (DTVECR)
b7
SWDTE
0
b6
DTVEC6
0
b5
DTVEC5
0
b4
DTVEC4
0
b3
DTVEC3
0
b2
DTVEC2
0
b1
DTVEC1
0
b0
DTVEC0
0
H'FF053D
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 SWDTE DTC software
activation
enable
0: Disables the DTC activation by software.
1: Enables the DTC activation by software.
Setting this bit to 1 activates DTC.
[Clearing conditions]
• When the DISEL bit is 0 and the specified
number of data transfers has not ended.
• When 0 is written to the DISEL bit after a
software-activated data transfer end interrupt
(SWDTEND) request has been sent to the CPU.
When the DISEL bit is 1 and data transfer has ended
or when the specified number of data transfers has
ended, this bit will not be cleared.
R/W
6 DTVEC6 R/W
5 DTVEC5 R/W
4 DTVEC4 R/W
3 DTVEC3 R/W
2 DTVEC2 R/W
1 DTVEC1 R/W
0 DTVEC0
DTC software
activation
vector 6 to 0
These bits specify a vector number for DTC
activation by software.
These bits specify a vector number for DTC software
activation.
The vector address is expressed as H'0400 + (vector
number × 2). For example, when DTVEC6 to
DTVEC0 = H'10, the vector address is H'0420.
When the bit SWDTE is 0, these bits can be written.
R/W
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.