Datasheet

Section 11 Data Transfer Controller (DTC)
Page 344 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Table 11.1 Correspondence between Interrupt Sources and DTCER
Bit
Register 7 6 5 4 3 2 1 0
DTCERA IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7
DTCERB IADEND_1 IADCMP_1 IADEND_2
*
1
IADCMP_2
*
1
ELC1FP ELC2FP
SCI3_1_RXI SCI3_1_TXI
DTCERC SCI3_2_RXI SCI3_2_TXI SCI3_3_RXI SCI3_3_TXI ⎯ ⎯ ⎯ ⎯
DTCERD IIC2/SSU_
RXI
IIC2/SSU_
TXI
⎯ ⎯ ITCMA*
2
ITCMB*
2
ITCMC*
2
ITCMD*
2
DTCERE ITDMA0_0 ITDMB0_0 ITDMC0_0 ITDMD0_0 ITDMA0_1 ITDMB0_1 ITDMC0_1 ITDMD0_1
DTCERF ITDMA1_2
*
3
ITDMB1_2
*
3
ITDMC1_2
*
3
ITDMD1_2
*
3
ITDMA1_3
*
3
ITDMB1_3
*
3
ITDMC1_3
*
3
ITDMD1_3
*
3
DTCERG ⎯ ⎯ ⎯ ITESC ITEMI ITEHR ITEDY ITEWK
DTCERH ⎯ ⎯ ⎯ ⎯ ITGMA ITGMB ⎯ ⎯
Notes: ⎯: Reserved bit
1. Supported only in the H8S/20223 and H8S/20235 Groups.
2. Supported only in the H8S/20103 and H8S/20115 Groups.
3. Not supported in the H8S/20103 and H8S/20115 Groups.