Datasheet

Section 11 Data Transfer Controller (DTC)
REJ09B0465-0300 Rev. 3.00 Page 343 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
11.2.7 DTC Enable Registers A to H (DTCERA to DTCERH)
b7
DTCEn7
0
b6
DTCEn6
0
b5
DTCEn5
0
b4
DTCEn4
0
b3
DTCEn3
0
b2
DTCEn2
0
b1
DTCEn1
0
b0
DTCEn0
0
H'FF0534 to H'FF053B
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 DTCEn7 R/W
6 DTCEn6 R/W
5 DTCEn5 R/W
4 DTCEn4 R/W
3 DTCEn3 R/W
2 DTCEn2 R/W
1 DTCEn1 R/W
0 DTCEn0
DTC activation
enable
0: A relevant interrupt source is not selected as a
DTC activation source.
1: A relevant interrupt source is selected as a DTC
activation source.
[Setting condition]
• Setting this bit to 1 specifies a relevant interrupt
source to a DTC activation source.
[Clearing conditions]
• When the DISEL bit in MRB is set to 1 and the
data transfer has ended.
• When the specified number of data transfers has
ended.
These bits are not automatically cleared when the
DISEL bit is 0 and the specified number of data
transfers has not ended.
• When 0 is written to DTCE after reading DTCE =
1.
R/W
Notes: n = A to H
DTCE bits with no corresponding interrupt are reserved. The write value should always be
0.
DTCER, which is comprised of DTCERA to DTCERH, is a register that specifies DTC activation
interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table
11.1. For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all
interrupts are masked, multiple activation sources can be set at one time (only at the initial setting)
by writing data after executing a dummy read on the relevant register.