Datasheet

Section 11 Data Transfer Controller (DTC)
Page 342 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
11.2.5 DTC Transfer Count Register A (CRA)
b15
bit15
⎯
b14
bit14
⎯
b13
bit13
⎯
b12
bit12
⎯
b11
bit11
⎯
b10
bit10
⎯
b9
bit9
⎯
b8
bit8
⎯
⎯
b7
bit7
⎯
b6
bit6
⎯
b5
bit5
⎯
b4
bit4
⎯
b3
bit3
⎯
b2
bit2
⎯
b1
bit1
⎯
b0
bit0
⎯
Bit:
Address:
Value after reset:
Bit:
Value after reset:
CRA designates the number of times that data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). In repeat mode, CRAH holds the number of transfers while
CRAL functions as an 8-bit transfer counter (1 to 256). In block transfer mode, CRAH holds the
size of blocks while CRAL functions as a block-size counter. CRAL is decremented by 1 every
time data is transferred, and the contents of CRAH are sent when the count value reaches H'00.
11.2.6 DTC Transfer Count Register B (CRB)
b15
bit15
⎯
b14
bit14
⎯
b13
bit13
⎯
b12
bit12
⎯
b11
bit11
⎯
b10
bit10
⎯
b9
bit9
⎯
b8
bit8
⎯
⎯
b7
bit7
⎯
b6
bit6
⎯
b5
bit5
⎯
b4
bit4
⎯
b3
bit3
⎯
b2
bit2
⎯
b1
bit1
⎯
b0
bit0
⎯
Bit:
Address:
Value after reset:
Bit:
Value after reset:
CRB is a 16-bit register that designates the number of times block data is to be transferred by the
DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
The CRB is not available in normal and repeat modes.