Datasheet

Section 11 Data Transfer Controller (DTC)
REJ09B0465-0300 Rev. 3.00 Page 337 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
11.2 Register Descriptions
DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
The above six registers cannot be directly accessed from the CPU. When the DTC activation
source is generated, the DTC reads from a set of register information that is stored in an on-chip
RAM to the corresponding DTC register information and transfers data. After the data transfer, it
writes a set of updated register information back to the RAM.
• DTC enable register A (DTCERA)
• DTC enable register B (DTCERB)
• DTC enable register C (DTCERC)
• DTC enable register D (DTCERD)
• DTC enable register E (DTCERE)
• DTC enable register F (DTCERF)
• DTC enable register G (DTCERG)
• DTC enable register H (DTCERH)
• DTC vector register (DTVECR)