Datasheet

Section 10 I/O Ports
Page 310 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
10.7.3 Port Data Register 9 (PDR9)
b7
PDR97
0
b6
PDR96
0
b5
PDR95
0
b4
PDR94
0
b3
PDR93
0
b2
PDR92
0
b1
PDR91
0
b0
PDR90
0
H'FFFFE8
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 PDR97 Port 97 data R/W
6 PDR96 Port 96 data R/W
5 PDR95 Port 95 data R/W
4 PDR94 Port 94 data R/W
3 PDR93 Port 93 data R/W
2 PDR92 Port 92 data R/W
1 PDR91 Port 91 data R/W
0 PDR90 Port 90 data
0: Low level
1: High level
PDR9 is a register that stores output data for port 9
pins. When PCR9 bits are set to 1, the values
stored in PDR9 are output.
When PDR9 is read while PCR9 bits are set to 1,
the values stored in PDR9 are read. If PDR9 is read
while PCR9 bits are cleared to 0, the pin states are
read regardless of the value stored in PDR9.
R/W