Datasheet

Section 10 I/O Ports
Page 292 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
10.4.3 Port Data Register 5 (PDR5)
b7
PDR57
0
b6
PDR56
0
b5
PDR55
0
b4
PDR54
0
b3
PDR53
0
b2
PDR52
0
b1
PDR51
0
b0
PDR50
0
H'FFFFE4
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 PDR57 Port 57 data R/W
6 PDR56 Port 56 data R/W
5 PDR55 Port 55 data R/W
4 PDR54 Port 54 data R/W
3 PDR53 Port 53 data R/W
2 PDR52 Port 52 data R/W
1 PDR51 Port 51 data R/W
0 PDR50 Port 50 data
0: Low level
1: High level
PDR5 is a register that stores output data for port 5
pins. When PCR5 bits are set to 1, the values
stored in PDR5 are output.
When PDR5 is read while PCR5 bits are set to 1,
the values stored in PDR5 are read. If PDR5 is read
while PCR5 bits are cleared to 0, the pin states are
read regardless of the value stored in PDR5.
R/W