Datasheet

Section 10 I/O Ports
Page 286 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
10.3.3 Port Data Register 3 (PDR3)
b7
PDR37
0
b6
PDR36
0
b5
PDR35
0
b4
PDR34
0
b3
PDR33
0
b2
PDR32
0
b1
PDR31
0
b0
PDR30
0
H'FFFFE2
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 PDR37 Port 37 data R/W
6 PDR36 Port 36 data R/W
5 PDR35 Port 35 data R/W
4 PDR34 Port 34 data R/W
3 PDR33 Port 33 data R/W
2 PDR32 Port 32 data R/W
1 PDR31 Port 31 data R/W
0 PDR30 Port 30 data
0: Low level
1: High level
PDR3 is a register that stores output data for port 3
pins. When PCR3 bits are set to 1, the values
stored in PDR3 are output.
When PDR3 is read while PCR3 bits are set to 1,
the values stored in PDR3 are read. If PDR3 is read
while PCR3 bits are cleared to 0, the pin states are
read regardless of the value stored in PDR3.
R/W