Datasheet

Section 10 I/O Ports
Page 280 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
10.2.3 Port Data Register 2 (PDR2)
b7
PDR27
0
b6
PDR26
0
b5
PDR25
0
b4
PDR24
0
b3
PDR23
0
b2
PDR22
0
b1
PDR21
0
b0
PDR20
0
H'FFFFE1
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 PDR27 Port 27 data R/W
6 PDR26 Port 26 data R/W
5 PDR25 Port 25 data R/W
4 PDR24 Port 24 data R/W
3 PDR23 Port 23 data R/W
2 PDR22 Port 22 data R/W
1 PDR21 Port 21 data R/W
0 PDR20 Port 20 data
0: Low level
1: High level
PDR2 is a register that stores output data for port 2
pins. When PCR2 bits are set to 1, the values
stored in PDR2 are output.
When PDR2 is read while PCR2 bits are set to 1,
the values stored in PDR2 are read. If PDR2 is read
while PCR2 bits are cleared to 0, the pin states are
read regardless of the value stored in PDR2.
R/W