Datasheet

Section 7 ROM
Page 192 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
3. Operating frequency
The operating frequency is calculated from the received input frequency and frequency
division ratio. The input frequency is the frequency of the clock signal supplied to the LSI,
whereas the operating frequency is the frequency at which the LSI actually operates. The
following formula is used for the calculation.
Operating frequency = input frequency/frequency division ratio
The obtained operating frequency is checked to see if it is within the range from the minimum
to maximum values of the operating frequency of the selected clock mode of the selected
device. If not, an operating frequency error is generated.
4. Bit rate
From the peripheral operating frequency (φ) and bit rate (B), the value (n) of the clock select
bits (CKS) in the serial mode register (SMR) and the value (N) in the bit rate register (BRR)
are calculated to determine the error. The error determined is checked to see if it is smaller
than 4%. If not, a bit-rate selection error is generated. The following formula is used for the
calculation.
Error (%) =
(N + 1) × B × 64 × 2
2n-1
φ × 10
6
× 100
- 1
When selection of the new bit rate is possible, the boot program returns an ACK code to the host
and then makes the necessary register settings to select the new bit rate. The host then transmits an
ACK code at the new bit rate and the boot program responds to it at the new bit rate.
Acknowledge H'06
• Acknowledge H'06 (1 byte): Acknowledgement of the new bit rate
Response H'06
• Response H'06 (1 byte): Response to acknowledgement of the new bit rate
Figure 7.9 shows the sequence of new bit-rate selection.