Datasheet

Section 7 ROM
REJ09B0465-0300 Rev. 3.00 Page 191 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
• Frequency division ratio 2 (1 byte): Frequency division ratio for the peripheral operating
frequency.
The negative numerical value by which the frequency is divided. (Example: H'FE (-2) when
the frequency is divided by two.)
• SUM (1 byte): Checksum
Response H'06
• Response H'06 (1 byte): Response to the new bit-rate selection command
The ACK code is returned when selection is possible.
Error response
H'BF ERROR
• Error response H'BF (1 byte): Error response to a new bit-rate selection command
• ERROR (1 byte): Error code
H'11: Checksum error
H'24: Bit-rate selection error indicating that the specified bit rate is not selectable.
H'25: Input frequency error indicating that the specified input frequency is not within the range
from the minimum to maximum values.
H'26: Frequency division ratio error indicating disagreement of frequency division ratios
H'27: Operating frequency error indicating that the specified operating frequency is not within
the range from the minimum to maximum values.
(4) Checking Received Data
The following describes how the received data is checked.
1. Input frequency
Clock source checking: The value of bit 15 indicates a clock source (the external clock or on-
chip oscillator).
Frequency checking: The value of the received input frequency (bits 14 to 0) is checked to see
if it is within the range from minimum to maximum values of the input frequency of the
selected clock mode of the selected device. If not, an input frequency error is generated.
2. Frequency division ratio
The value of the received frequency division ratio is checked to see if it corresponds to the
frequency division ratio value of the selected clock mode of the selected device. If not, a
frequency division ratio error is generated.