Datasheet

Section 7 ROM
REJ09B0465-0300 Rev. 3.00 Page 171 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
This LSI
Flash memory
On-chip RAM
RxD (P21)
TxD (P22)
SCI
On-chip control-command
analysis execution software
Control commands and
programming data
Returned response
Host
Programming tool
and
programming data
Figure 7.2 System Configuration in Boot Mode
(1) Serial Interface Settings by Host
SCI3_1 is set to asynchronous mode, in which the serial transmission/reception format is set to 8-
bit data, one stop-bit, and no parity.
When this LSI enters boot mode, the built-in boot program is initiated. When the boot program is
initiated, this LSI measures the low-level period of asynchronous serial communication data
(H'00) transmitted continuously from the host. This LSI then calculates the bit rate of transmission
from the host, and adjusts the SCI bit rate so that it should match that of the host.
After completing the bit rate adjustment, this LSI transmits one H'00 byte to the host to signal
completion of bit rate adjustment. When successfully having received this completion signal, the
host should transmit one H'55 byte to this LSI. When not, boot mode should be initiated again.
Table 7.4 shows the automatically adjustable bit rates for the host.
Start bit Stop bitD0 D1 D2 D3 D4 D5 D6 D7
Measures low-level period (9 bits) (data: H'00) High-level period
of 1 or more bits
Figure 7.3 Automatic Adjustment of Bit Rates