Datasheet

Section 7 ROM
Page 160 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Item EW0 Mode EW1 Mode
CPU state during auto-
programming and auto-erasure
Operating state Hold state (I/O ports retain the
states in which they have been
before the command is
executed.)
Flash memory state detection Read the FMPRSF, FMERSF, and FMEBSF bits in FLMSTR in a
program.
Conditions of transition to erase-
suspend state
Both the FMSPEN and
FMSPREQ bits in FLMCR2 are
set to 1.
Or, both the FMSPEN and
FMISPE bits in FLMCR2 are set
to 1 and an interrupt is
requested.
The FMSPEN bit in FLMCR2 is
set to 1 and an interrupt is
requested.
Conditions of Interrupt
generation
• The flash memory returns
from the busy state to the
ready state*
1
.
• The user ROM area is read
in the busy state*
1
.
Use of interrupts prohibited.
Usage of DTC Usable*
2
Usable*
2
*
3
Notes: 1. To avoid the generation of access to the user ROM area, set VOFR so that the variable
vectors and interrupt processing routines are allocated to RAM.
2. Allocate DTC vectors and processing routines to RAM. Do not use the DTC for access
to the user ROM area during E/W processing. If this is ignored, values read will be
invalid.
3. Do not use the DTC if the reprogramming-control program is allocated to RAM.