Datasheet
Section 6 Power-Down Modes
Page 150 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
6.2.3 Standby Mode
When a SLEEP instruction is executed in active mode with the SSBY bit = 1 in LPCR1, a
transition to standby mode is made. In standby mode, clock oscillation is stopped and thus the
CPU, DTC, and all the on-chip peripheral modules (except timer RE and WDT) are stopped.
However, as long as the rated voltage is supplied, the following contents are retained: the CPU
registers, the registers of some on-chip peripheral modules, and on-chip RAM. Additionally, on-
chip RAM contents will be retained as long as the voltage rated as the RAM data retention voltage
is provided. The I/O ports go to the high-impedance state.
When an interrupt is requested, standby mode is canceled causing a transition to active mode and
interrupt exception handling starts. Standby mode cannot be canceled if the I bit in CCR is 1 or the
requested interrupt is masked by the interrupt enable bit. After standby mode is canceled, the high-
speed or low-speed clock is selected as the system clock source depending on the STBYRS bit
setting in LPCR1.
When the RES pin is driven low or any other internal reset occurs, standby mode is canceled
causing a transition to the reset state.
6.3 Bus Master Clock Division Function
In active or sleep mode, the operating clock for the CPU, DTC, on-chip ROM, and on-chip RAM
can be divided independently of the clock supplied to the peripheral modules. Using a divided
clock can reduce power consumption.
The operating clock φs for the bus masters and the on-chip ROM and on-chip RAM can be
selected from among φ, φ/2, φ/4, φ/8, φ/16, and φ/32 according to the PHIS[2:0] setting in LPCR3.
6.3.1 Reset States
For reset states, see section 3.3, Reset.