Datasheet

Section 6 Power-Down Modes
Page 146 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
• MSTTMRA bit (timer RA module standby)
When this bit is set to 1, timer RA enters the standby state.
• MSTTMRB bit (timer RB module standby)
When this bit is set to 1, timer RB enters the standby state.
• MSTTMRC bit (timer RC module standby)
When this bit is set to 1, timer RC enters the standby state.
Timer RC is not available on the H8S/20203, H8S/20223, H8S/20215, and H8S/20235
Groups; this bit is reserved on these devices. For a write-access, write 1 to this bit.
• MSTTMRD1 bit (timer RD unit 0 module standby)
When this bit is set to 1, timer RD unit 0 enters the standby state.
• MSTTMRD2 bit (timer RD unit 1 module standby)
When this bit is set to 1, timer RD unit 1 enters the standby state.
Timer RD unit 1 is not available on the H8S/20103 and H8S/20115 Groups; this bit is reserved
on the device. For a write-access, write 1 to this bit.
• MSTTMRG bit (timer RG module standby)
When this bit is set to 1, timer RG enters the standby state.
• MSTTMRE bit (timer RE module standby)
When this bit is set to 1, timer RE enters the standby state. Note that if the φsub is selected as
the count clock in realtime clock mode or output-compare mode, timer RE operates regardless
of the setting of this bit but the timer RE registers cannot be accessed.