Datasheet

Section 6 Power-Down Modes
Page 144 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
6.1.3 Module Standby Control Register 2 (MSTCR2)
b7
MSTSCI3_1
1
b6
MSTSCI3_2
1
b5
MSTSCI3_3
1
b4
⎯
1
b3
⎯
1
b2
MSTICSU
1
b1
⎯
1
b0
⎯
1
H'FFFFDD
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 MSTSCI3_1 SCI3 channel 1
module standby
0: Operating state
1: Standby state
R/W
6 MSTSCI3_2 SCI3 channel 2
module standby
0: Operating state
1: Standby state
R/W
5 MSTSCI3_3 SCI3 channel 3
module standby
0: Operating state
1: Standby state
R/W
4, 3 ⎯ Reserved These bits are read as 1. The write value should
be 1.
⎯
2 MSTICSU IIC2/SSU
module standby
0: Operating state
1: Standby state
R/W
1, 0 ⎯ Reserved These bits are read as 1. The write value should
be 1.
⎯
Notes: 1. When a peripheral module is in the module standby state, the registers of the module
cannot be accessed.
2. When writing to this register, write 1s to the reserved bits.
• MSTSCI3_1 (SCI3 channel 1 module standby)
When this bit is set to 1, SCI3 channel 1 enters the standby state.
• MSTSCI3_2 (SCI3 channel 2 module standby)
When this bit is set to 1, SCI3 channel 2 enters the standby state.
• MSTSCI3_3 (SCI3 channel 3 module standby)
When this bit is set to 1, SCI3 channel 3 enters the standby state.
• MSTICSU (IIC2/SSU module standby)
When this bit is set to 1, the IIC2 or SSU enters the standby state.