Datasheet

Section 5 Clock Pulse Generator
Page 130 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
CLKA
CLKB
SELA
SELB
φbase
Operation at CLKA Oscillation settling wait time
[Legend]
CLKA: Clock A
CLKB: Clock B
SELA: CLKA select signal
SELB: CLKB select signal
φbase: System base clock
Note: The oscillation settling time differs according to the clock source.
Operation at CLKB
Figure 5.7 Timing of Clock Source Switching
(When the switching destination clock source is stopped)
Oscillation stabilization wait time varies with switching destination clock sources. If the
destination clock is φosc, wait time is specified by the STS[3:0] bit of the OSCCSR. For
oscillation stabilization wait time values, see table 5.2.
During oscillation stabilization wait time, the φbase stops; therefore, any module that operates
with the φbase as a base, including the bus master, stops. The register retains the pre-switching
value.