Datasheet

Section 5 Clock Pulse Generator
REJ09B0465-0300 Rev. 3.00 Page 123 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
5.3 Operation of Selection of System Reference Clock
After a reset, this LSI enters active mode operating in low-speed clocks. The user, by means of
software, can change the system reference clock from a low-speed OCO clock to the main
oscillator clock or a sub-oscillator clock.
Figure 5.2 shows a transition diagram between system reference clock states. Table 5.3 shows
conditions under which clock sources can be switched.
Reset state
Reset released
Operation at
low-speed OCO clock
PHIBSEL=0
PHIHSEL=X
PHILSEL=0
Operation at sub-clock
PHIBSEL=0
PHIHSEL=X
PHILSEL=1
Operation at
main oscillator clock
PHIBSEL=1
PHIHSEL=1
PHILSEL=X
[Legend]
X: Don't care
The LSI operates on φlow. The LSI operates on φhigh.
Figure 5.2 Transition Diagram between LSI System Reference Clock States