Datasheet
Section 5 Clock Pulse Generator
Page 122 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
If the φosc is already oscillating stably or the φosc is an external clock input, wait time can be
selected from 16 states (STS[3:0]=B'0000).
Table 5.2 Relationship between Operation Frequency and Number of Wait States
Bit Operation Frequency
STS3 STS2 STS1 STS0
Number of
Wait States
20 MHz 16 MHz 10 MHz 8 MHz 4 MHz
0 0 0 0 16 states 0.00 0.00 0.00 0.00 0.00
0 0 0 1 32 states 0.00 0.00 0.00 0.00 0.01
0 0 1 0 64 states 0.00 0.00 0.01 0.01 0.02
0 0 1 1 128 states 0.01 0.01 0.01 0.02 0.03
0 1 0 0 256 states 0.01 0.02 0.03 0.03 0.06
0 1 0 1 512 states 0.03 0.03 0.05 0.06 0.13
0 1 1 0 1024 states 0.05 0.06 0.10 0.13 0.26
0 1 1 1 2048 states 0.10 0.13 0.20 0.26 0.51
1 0 0 0 4096 states 0.20 0.26 0.41 0.51 1.02
1 0 0 1 8192 states 0.41 0.51 0.82 1.02 2.05
1 0 1 0 16384 states 0.82 1.02 1.64 2.05 4.10
1 0 1 1 32768 states 1.64 2.05 3.28 4.10 8.19
1 1 0 0 65536 states 3.28 4.10 6.55 8.19 16.38
1 1 0 1 131072 states 6.55 8.19 13.11 16.38 32.77
1 1 1 0 262144 states 13.11 16.38 26.21 32.77 65.54
1 1 1 1 262144 states 13.11 16.38 26.21 32.77 65.54