Datasheet

Section 5 Clock Pulse Generator
Page 120 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
4 SLEEPINT Sleep mode
interrupt
generation flag
0: No interrupt has occurred in sleep mode.
1: An interrupt has occurred in sleep mode.
[Setting condition]
When an interrupt is generated in sleep mode.
[Clearing condition]
When an interrupt is generated in states other
than sleep mode.
R
3 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯
2 to 0 PHIS[2:0] Bus master
operation clock
φs select
000: φ
001: φ/2
010: φ/4
011: φ/8
100: φ/16
101: φ/32
110: Setting prohibited
111: Setting prohibited
R/W
Note: A MOV instruction should be used to write to this register.
• WI bit (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bits 2 to 0 in this register can be written to when this bit is 1.
• STBYINT bit (standby mode interrupt generation flag)
This bit is set to 1 when an interrupt is generated in standby mode. This bit is cleared to 0
when an interrupt is generated in the other state.
• SLEEPINT bit (sleep mode interrupt generation flag)
This bit is set to 1 when an interrupt is generated in sleep mode. This bit is cleared to 0 when
an interrupt is generated in the other state.
• PHIS[2:0] bits (bus master operation clock φs select)
Selects a clock source for the bus master operation clock φs to be used in active mode or sleep
mode. The clock is changed immediately after these bits are set.