Datasheet

Section 5 Clock Pulse Generator
REJ09B0465-0300 Rev. 3.00 Page 119 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
• WI (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
• WE bit (write enable)
Bits 2 to 0 in this register can be written to when this bit is 1.
• PHI2 bit to PHI0 bit (system clock φ select)
Selects a clock source for the system clock φ to be used in active mode or sleep mode. The
clock is changed immediately after this bit is set.
5.2.5 Power-Down Control Register 3 (LPCR3)
b7
WI
1
b6
WE
0
b5
STBYINT
0
b4
SLEEPINT
0
b3
⎯
0
b2
0
b1
PHIS[2:0]
0
b0
0
H'FF06D3
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 WI Write inhibit 0: Writing is permitted.
1: Writing is inhibited.
W
6 WE Write enable 0: Writing is disabled.
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE at
the same time.
[Clearing condition]
When 0 is written to WI and WE at the same time.
R/W
5 STBYINT Standby mode
interrupt
generation flag
0: No interrupt has occurred in standby mode.
1: An interrupt has occurred in standby mode.
[Setting condition]
When an interrupt is generated in standby mode.
[Clearing condition]
When an interrupt is generated in states other
than standby mode.
R