Datasheet

Section 5 Clock Pulse Generator
Page 118 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
• STBYRS bit (φ source select for recovery from standby mode)
Selects a clock source to be used when a transition is made from standby mode to active mode.
• PHIBSEL bit (φbase clock source select)
Selects a clock source for the φbase to be used in active mode or sleep mode.
5.2.4 Power-Down Control Register 2 (LPCR2)
b7
WI
1
b6
WE
0
b5
⎯
0
b4
⎯
0
b3
⎯
0
b2
0
b1
0
b0
0
H'FF06D2
PHI[2:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 WI Write inhibit 0: Writing is permitted.
1: Writing is inhibited.
W
6 WE Write enable 0: Writing is disabled.
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE at
the same time.
[Clearing condition]
When 0 is written to WI and WE at the same time.
R/W
5 to 3 ⎯ Reserved These bits are read as 0. The write value should
be 0.
⎯
2 to 0 PHI[2:0] System clock φ
select
000: φbase
001: φbase/2
010: φbase/4
011: φbase/8
100: φbase/16
101: φbase/32
110: φbase/64
111: φbase/128
R/W
Note: A MOV instruction should be used to write to this register.