Datasheet

Section 5 Clock Pulse Generator
REJ09B0465-0300 Rev. 3.00 Page 115 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Bit Symbol Bit Name Description R/W
2, 1 SUBNC
[1:0]*
φsub noise
canceler
sampling
function
setting
00: The sampling circuit is disabled.
01: Sampling is performed at φbase/4.
10: Sampling is performed at φbase/16.
11: Setting prohibited
R/W
0 Reserved This bit is read as 0. The write value should be 0.
Notes: A MOV instruction should be used to write to this register.
* Only enable the sampling circuit after completion of switching of the system clock from
φloco to φosc. If the sampling circuit is enabled while the system clock is φloco, the
supply of φ subclock will be stopped during the period of waiting for stable φosc
oscillation when the system clock is switched from φloco to φosc.
Furthermore, if an application is also using the sampling circuit of the noise canceler for
the φ subclock signal in the period of switching of the system clock signal between φlow
and φosc, disable the sampling circuit of the noise canceler for the φ subclock signal
while φlow remains in use as the system clock signal.
WI bit (write inhibit)
This register can be written to only when this bit is 0. This bit is always read as 1.
WE bit (write enable)
Bits 5, 4, 2, and 1 in this register can be written to when this bit is 1.
PHIHSEL bit (φhigh clock source select)
This bit is 1 when 0 is written to the WI bit in BAKCR at CKSWIF = 0 and WE = 1 and then 1
is written to this bit.
PHILSEL bit (φlow clock source select)
When 0 is written to WI and 1 is written to this bit at WE = 1, this bit is 1.
When 0 is written to WI and this bit at WE = 1, this bit is 0.
SUBNC[1:0] bits (φsub noise canceler sampling function setting)
Selects a sampling clock for the subclock oscillator noise canceler. Enable the sampling circuit
when φsub is selected as a clock source for the timer RE, timer RA, and watchdog timer.
Note: The frequency of the low-speed on-chip oscillator varies greatly according to the power
supply voltage and operating temperature. In designing application systems, allow
sufficient margins for frequency variation.