Datasheet

Section 5 Clock Pulse Generator
Page 114 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
5.2.2 System Clock Control Register (SYSCCR)
b7
WI
1
b6
WE
0
b5
PHIHSEL
0
b4
PHILSEL
0
b3
⎯
0
b2
0
b1
0
b0
⎯
0
H'FF06D0
SUBNC[1:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 WI Write inhibit 0: Writing is permitted.
1: Writing is inhibited.
W
6 WE Write enable 0: Writing is disabled.
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE at the
same time.
[Clearing condition]
When 0 is written to WI and WE at the same time.
R/W
5 PHIHSEL φhigh clock
source select
0: Setting prohibited
1: φosc
[Setting condition]
When 1 is written to this bit while CKSWIF in BAKCR
is 0.
R/W
4 PHILSEL φlow clock
source select
0: φloco
1: φsub
R/W
3 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯