Datasheet

Section 5 Clock Pulse Generator
Page 112 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
5.2.1 Backup Control Register (BAKCR)
b7
WI
1
b6
WE
0
b5
OSCBAKE
0
b4
BAKCKSEL
0
b3
CKSWIE
0
b2
CKSWIF
0
b1
OSCHLT
0
b0
⎯
0
H'FF06D4
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 WI Write inhibit 0: Writing is permitted.
1: Writing is inhibited.
W
6 WE Write enable 0: Writing is disabled.
1: Writing is enabled.
[Setting condition]
When 0 is written to WI and 1 is written to WE at the
same time.
[Clearing condition]
When 0 is written to WI and WE at the same time.
R/W
5 OSCBAKE External clock
backup enable
0: External clock backup is disabled.
1: External clock backup is enabled.*
R/W
4 BAKCKSEL Backup
destination clock
source select
0: φlow
1: Setting prohibited
R/W
3 CKSWIE Clock switching
interrupt enable
0: Interrupt requests are disabled.
1: Interrupt requests are enabled.
R/W
2 CKSWIF Clock switching
interrupt flag
0: A clock switching interrupt request has not been
generated.
1: A clock switching interrupt request has been
generated.
[Setting condition]
When the system clock for the LSI is switched from
φosc to φlow while OSCBAKE is 1.
[Clearing condition]
When 1 is read from the bit and then 0 is written to
the same bit.
R/W