Datasheet

Section 4 Interrupt Controller
REJ09B0465-0300 Rev. 3.00 Page 101 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Yes
Program execution status
Interrupt generated
NMI
IFMBSYA
*
Level 2 interrupt
Mask level 1
or below
Level 3 interrupt
Mask level 2
or below
Save PC, CCR, and EXR
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Retained
Level 1 interrupt
Mask level 0
Yes
Yes
No
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No
No
Yes
Note: * Access interrupt when flash memory busy.
Figure 4.4 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2