Datasheet

Section 4 Interrupt Controller
Page 98 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
4.5 Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by INTCR. Table 4.4 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 4.4 Interrupt Control Modes
Interrupt
Control Mode
Priority Setting
Registers
Interrupt
Mask Bits Description
0 Default I The priorities of interrupt sources are fixed at
the default settings.
Interrupt sources except for NMI is masked by
the I bit.
2 IPR I1 and I0 Four priority levels except for NMI can be set
with IPR.
Four-level interrupt mask control is performed
by bits I1 and I0.
4.5.1 Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit in CCR of the
CPU. Figure 4.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
pending. If the I bit is cleared, an interrupt request is accepted.
3. When interrupt requests are sent to the interrupt controller, the highest-ranked interrupt request
according to the priority system is accepted, and other interrupt requests are retained.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. The I bit in CCR is set to 1. This masks all interrupts except NMI.
7. The CPU generates a vector address for the accepted interrupt request and starts execution of
the interrupt handling routine at the address indicated by the contents of the start address in the
vector table.