Datasheet

Section 4 Interrupt Controller
Page 88 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
4.2.8 Event Link Interrupt Control Status Register (ELCSR)
b7
⎯
0
b6
⎯
0
b5
⎯
0
b4
⎯
0
b3
ELIE2
0
b2
ELIE1
0
b1
ELF2
0
b0
ELF1
0
H'FF0528
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7 to 4 ⎯ Reserved These bits are read as 0. The write value should
be 0.
⎯
3 ELIE2 ELC interrupt 2
enable
0: ELF2 interrupts are disabled.
1: ELF2 interrupts are enabled.
R/W
2 ELIE1 ELC interrupt 1
enable
0: ELF1 interrupts are disabled.
1: ELF1 interrupts are enabled.
R/W
1 ELF2 ELC interrupt
flag 2
[Setting condition]
• When the event selected by ELSR30 occurs*
1
[Clearing conditions]
• When 1 is read from this bit and then 0 is
written to the same bit.
• When the DTC is activated by an ELF2
interrupt, and the DISEL bit in MRB of the DTC
is 0.*
2
R/W
0 ELF1 ELC interrupt
flag 1
[Setting condition]
• When the event selected by ELSR12 occurs*
1
[Clearing conditions]
• When 1 is read from this bit and then 0 is
written to the same bit.
• When the DTC is activated by an ELF1
interrupt, and the DISEL bit in MRB of the DTC
is 0.*
2
R/W
Notes: 1. For details, see section 12, Event Link Controller.
2. When the DTC is activated by an ELF1 or ELF2 interrupt, the event link source module
is not affected.