Datasheet

Section 4 Interrupt Controller
REJ09B0465-0300 Rev. 3.00 Page 87 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
4.2.7 Interrupt Vector Offset Register (VOFR)
b15
bit15
0
b14
bit14
0
b13
bit13
0
b12
bit12
0
b11
bit11
0
b10
bit10
0
b9
bit9
0
b8
bit8
0
H'FF0526
b7
bit7
0
b6
bit6
0
b5
bit5
0
b4
bit4
0
b3
bit3
0
b2
bit2
0
b1
bit1
0
b0
bit0
0
Address:
Bit:
Value after reset:
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
bit2 bit1 bit0
MSB LSB
00
0000000
0
VOFR
Interrupt vector
base address
Vector address
+
VOFR is a 16-bit readable/writable register that sets an offset for an interrupt vector address.
Interrupt vector areas other than the trace interrupt area and trap instruction interrupt area can be
varied with the offset. The upper 13 bits are used to set the offset for the interrupt vector address
(A23 to A11). Bits 2 to 0 are reserved. The write value should always be 0. This register also can
be accessed in 8-bit units.
The vector address can be obtained by adding the VOFR value to the interrupt vector base address
as shown above, except for the trace interrupt and trap instruction interrupt.
This register is initialized to H'0000 by a reset.
Note: When the DTC is used while the interrupt vector offset register (VOFR) holds an offset-
address setting, the VOFR setting has no effect. The DTC refers to the vector definition in
the vector address area defined by the initial value (H'0000) of VOFR, which leads to the
execution of exception processing.
Whenever the DTC is used, set the VOFR to H'0000 (its default value).