Datasheet

Section 4 Interrupt Controller
REJ09B0465-0300 Rev. 3.00 Page 79 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
• ADTRG1 and ADTRG0 bits (ADTRG2 and ADTRG1 edge select)
These bits select the input edge for the ADTRG2 and ADTRG1 pins.
4.2.2 Interrupt Priority Registers A to I (IPRA to IPRI)
• IPRA to IPRK
b7
1
b6
1
b5
1
b4
1
b3
1
b2
1
b1
1
b0
1
H'FF0529 to H'FF0531
IPRn[7:6] IPRn[5:4] IPRn[3:2] IPRn[1:0]
(n = A to I)
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7
6
IPRn[7:6]
Interrupt priority
7 and 6
00: Priority level 0 (lowest)
01: Priority level 1
10: Priority level 2
11: Priority level 3 (highest)
R/W
5
4
IPRn[5:4]
Interrupt priority
5 and 4
00: Priority level 0 (lowest)
01: Priority level 1
10: Priority level 2
11: Priority level 3 (highest)
R/W
3
2
IPRn[3:2]
Interrupt priority
3 and 2
00: Priority level 0 (lowest)
01: Priority level 1
10: Priority level 2
11: Priority level 3 (highest)
R/W
1
0
IPRn[1:0]
Interrupt priority
1 and 0
00: Priority level 0 (lowest)
01: Priority level 1
10: Priority level 2
11: Priority level 3 (highest)
R/W
[Legend]
n = A to I
• IPR7 to IPR0 bits (Interrupt priority 7 to 0)
IPR are nine 8-bit readable/writable registers that set priorities (levels 3 to 0) for interrupt sources
other than Nonmaskable interrupt request (NMI). The correspondence between interrupt sources
and IPR settings is shown in table 4.2. Setting a value in the range from H'0 to H'3 in the 2-bit
groups of bits 7 and 6, 5 and 4, 3 and 2, and, 1 and 0 determines the priority of the corresponding
interrupt requests.