Datasheet

Section 4 Interrupt Controller
Page 78 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
4.2.1 Interrupt Control Register (INTCR)
b7
⎯
0
b6
⎯
0
b5
0
b4
0
b3
NMIEG
0
b2
ADTRG1
0
b1
ADTRG0
0
b0
⎯
0
H'FF0520
INTM[1:0]
Bit:
Address:
Value after reset:
Bit Symbol Bit Name Description R/W
7
6
⎯ Reserved These bits are read as 0. The write value should
be 0.
⎯
5
4
INTM[1:0] Interrupt control
select mode 1
and 0
00: Interrupt control mode 0
Interrupts are controlled by the I bit.
01: Setting prohibited
10: Interrupt control mode 2
Interrupts are controlled by bits I1 and I0, and
IPR.
11: Setting prohibited
R/W
3 NMIEG NMI edge select 0: Interrupt request is generated at falling edge of
NMI input.
1: Interrupt request is generated at rising edge of
NMI input.
R/W
2 ADTRG1 ADTRG2 edge
select
0: AD2 conversion is started at falling edge of
ADTRG2 input.
1: AD2 conversion is started at rising edge of
ADTRG2 input.
R/W
1 ADTRG0 ADTRG1 edge
select
0: AD1 or AD2 conversion is started at falling edge
of ADTRG1 input.
1: AD1 or AD2 conversion is started at rising edge
of ADTRG1 input.
R/W
0 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯
• INTM1 and INTM0 bits (interrupt control select mode 1 and 0)
These bits select the interrupt control mode for the interrupt controller.
• NMIEG bit (NMI edge select)
Selects the input edge for the NMI pin.