Datasheet

Section 4 Interrupt Controller
REJ09B0465-0300 Rev. 3.00 Page 75 of 982
Sep 17, 2010
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group
Section 4 Interrupt Controller
4.1 Features
• Two interrupt control modes
Either of the two interrupt control modes can be selected by means of the INTM1 and INTM0
bits in the interrupt control register (INTCR).
• Priorities settable with IPR
An interrupt priority register (IPR) is provided for setting interrupt priorities. Four priority
levels can be set for each module for all interrupts except NMI. NMI and some flash memory
interrupts are assigned the highest priority level of 3, and can be accepted at all times.
• Independent vector addresses
Most interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Nine external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
can be selected for NMI. Falling edge, rising edge, or both edges can be selected independently
for IRQ7 to IRQ0.
• DTC control
DTC activation is performed by means of interrupt requests.