Datasheet

REJ09B0465-0300 Rev. 3.00 Page 975 of 982
Sep 17, 2010
Item Page Revision (See Manual for Details)
Section 23 Hardware LIN
23.3 Operation
23.3.3 Bus Conflict Detection
Function
811 Deleted
The hardware LIN interface can detect bus conflicts if
SCI3_1 is enabled for transmission (TE bit in SCR3_1
register is 1).
Section 24 A/D Converter
24.1 Features
Figure 24.2 Block Diagram of
A/D Converter (Unit 2)
817 Added
+
AN0_2
AN1_2
AN2_2
AN3_2
ADTRG2
ADTRG1
CMPI interrupt signal
AD interrupt signal
Conversion start trigger from timer RC or RD
Sample-and-hold circuit
Comparator
Multiplexer
Control circuit
Table 24.1 Pin Configuration 818 Notes amended
Notes: 1. Not supported in the H8S/20103 and H8S/20115
Groups.
2. Supported only in the H8S/20223 and
H8S/20235 Groups.
3. This pin can also be used as the trigger-signal
input for unit 2.
24.2 Register Description 819 Amended
Unit 1:
• Compare control/status register (CMPCSR)
Unit 2:
• Compare control/status register_2 (CMPCSR_2)
24.2.2 A/D Control/Status
Register (ADCSR)
823 Added
• ADST bit (A/D start)
…
To select AN0 and AN0_2 as the channels for
conversion, specify analog input operation for the pins
by setting the PMRA2 and PMRA3 bits.
24.2.7 Compare Voltage
Registers H and L
(CMPVALH and CMPVALL)
830 Register name amended