Datasheet

Page 974 of 982 REJ09B0465-0300 Rev. 3.00
Sep 17, 2010
Item Page Revision (See Manual for Details)
21.6.4 Note on Access to ICE
in ICCR1 and IICRST in
ICCR2 during I
2
C Bus
Operation
766 Added
Section 22 Synchronous
Serial Communication Unit
(SSU)
22.2 Register Descriptions
22.2.9 SS Transmit Data
Register (SSTDR)
780 Added
… If the MLS bit in SSMR is set to 1 and when the data is
written to SSTDR, the MSB/LSB inverted data is read.
SSTDR is initialized to H'FF. In standby mode, SSTDR is
initialized.
22.2.10 SS Shift Register
(SSTRSR)
780 Deleted
SSTRSR is a shift register that transmits and receives
serial data. When transmit data is transferred from SSTDR
to SSTRSR, bit 0 in SSTDR is transferred to bit 0 in
SSTRSR while the MLS bit in SSMR is 0 (LSB-first
transfer) and bit 7 in SSTDR is transferred to bit 0 in
SSTRSR while the MLS bit in SSMR is 1 (MSB-first
transfer). SSTRSR is not directly readable or writable from
the CPU. In standby mode, SSTRSR is initialized.
22.3 Operation
22.3.2 Relationship between
Clock Polarity and Phase,
and Data
781 Amended
…
MSB-first transfer or LSB first transfer can be selected by
the setting of the MLS bit in SSMR. When the MLS bit is 1,
transfer is started from LSB to MSB. When the MLS bit is 0,
transfer is started from MSB to LSB.
22.3.6 Operation in Four-Line
Bus Communication Mode
791 Amended
…
In four-line bus communication mode, transfer is performed
in MSB-first order while the MLS bit in SSMR is 0.
Figure 22.10 Initialization in
Four-Line Bus
Communication Mode
792 Amended
[1]
Clear MLS in SSMR to 0 and
set CPOS and CPHS, and
CKS2 to CKS0 inSSCRH
[1] The MLS bit is cleared to 0 for MSB-first transfer.
The clock polarity and phase are set in the
CPOS and CPHS bits.