Datasheet

Page x of xxvi
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 57
2.7.8 Memory Indirect—@@aa:8 ................................................................................... 58
2.7.9 Effective Address Calculation ................................................................................ 59
2.8 Processing States.................................................................................................................. 61
2.9 Usage Notes ......................................................................................................................... 63
2.9.1 TAS Instruction ...................................................................................................... 63
2.9.2 STM and LDM Instructions.................................................................................... 63
2.9.3 Note on Bit Manipulation Instructions.................................................................... 63
2.9.4 EEPMOV Instruction.............................................................................................. 64
Section 3 Exception Handling .............................................................................65
3.1 Exception Handling Types and Priority............................................................................... 65
3.2 Exception Handling Sources and Vector Table ................................................................... 65
3.3 Reset .................................................................................................................................... 66
3.3.1 Reset Sources.......................................................................................................... 66
3.3.2 Reset Exception Handling ...................................................................................... 69
3.3.3 Interrupts immediately after Reset.......................................................................... 70
3.3.4 On-Chip Peripheral Functions after Reset Release................................................. 70
3.4 Trace Exception Handling ................................................................................................... 71
3.5 Interrupt Exception Handling .............................................................................................. 72
3.6 Trap Instruction Exception Handling................................................................................... 72
3.7 Stack Status after Exception Handling................................................................................. 73
3.8 Usage Note........................................................................................................................... 74
Section 4 Interrupt Controller..............................................................................75
4.1 Features................................................................................................................................ 75
4.2 Register Descriptions...........................................................................................................77
4.2.1 Interrupt Control Register (INTCR) ....................................................................... 78
4.2.2 Interrupt Priority Registers A to I (IPRA to IPRI).................................................. 79
4.2.3 IRQ Enable Register (IER) ..................................................................................... 81
4.2.4 IRQ Sense Control Register H and L (ISCRH and ISCRL) ................................... 82
4.2.5 IRQ Status Register (ISR)....................................................................................... 85
4.2.6 IRQ Noise Canceler Control Register (INCCR)..................................................... 86
4.2.7 Interrupt Vector Offset Register (VOFR) ............................................................... 87
4.2.8 Event Link Interrupt Control Status Register (ELCSR) ......................................... 88
4.3 Interrupt Sources.................................................................................................................. 89
4.3.1 External Interrupt sources....................................................................................... 89
4.3.2 Internal Interrupts ................................................................................................... 90
4.4 Interrupt Exception Handling Vector Table......................................................................... 91