Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (14x14) 16-Bit 20 MHz I/O number 69

User's Manual

H8S/20103, H8S/20203, H8S/20223,

H8S/20115, H8S/20215, H8S/20235 Group

User’s Manual: Hardware

Renesas 16-Bit Single-Chip Microcomputer

H8S Family / H8S/Tiny Series

H8S/20103 R4F20103

H8S/20203 R4F20203

H8S/20223 R4F20223

H8S/20115 R4F20115

H8S/20215 R4F20215

H8S/20235 R4F20235

www.renesas.com

The revision list summarizes the locations of

revisions and additions. Details should always

be checked by referring to the relevant text.

Rev.3.00 Se

2010

Summary of content (1012 pages)

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User's Manual 16 The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group User’s Manual: Hardware Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/Tiny Series H8S/20103 R4F20103 H8S/20203 R4F20203 H8S/20223 R4F20223 H8S/20115 R4F20115 H8S/20215 R4F20215 H8S/20235 R4F20235 www.renesas.com Rev.3.
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Page ii of xxvi
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Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. 2.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
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How to Use This Manual 1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers.
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2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below. (1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name".
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3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below.
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4. Description of Abbreviations The abbreviations used in this manual are listed below.
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Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 1.1.1 Applications.............................................................................................................. 1 1.1.2 Overview of Functions......................................................................
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2.8 2.9 2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC) ...................................... 57 2.7.8 Memory Indirect—@@aa:8 ................................................................................... 58 2.7.9 Effective Address Calculation ................................................................................ 59 Processing States.................................................................................................................. 61 Usage Notes .....................
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4.5 4.6 Interrupt Control Modes and Interrupt Operation ................................................................ 98 4.5.1 Interrupt Control Mode 0........................................................................................ 98 4.5.2 Interrupt Control Mode 2...................................................................................... 100 4.5.3 Interrupt Exception Handling Sequence ............................................................... 102 4.5.4 Interrupt Response Time..
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Section 6 Power-Down Modes.......................................................................... 141 6.1 6.2 6.3 6.4 6.5 Register Descriptions ......................................................................................................... 142 6.1.1 Power-Down Control Registers 1, 2, and 3 (LPCR1, LPCR2, LPCR3) ............... 142 6.1.2 Module Standby Control Register 1 (MSTCR1) .................................................. 142 6.1.3 Module Standby Control Register 2 (MSTCR2) ..........
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Section 9 Peripheral I/O Mapping Controller....................................................237 9.1 9.2 Register Descriptions ......................................................................................................... 239 9.1.1 Peripheral Function Mapping Register Write-Protect Register (PMCWPR)........ 240 9.1.2 Port Group 1 Peripheral Function Mapping Registers 1 to 4 (PMCRn1 to PMCRn4 (n = 1, 2, 3, 5, and 6)) ...................................................... 241 9.1.
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10.6 10.7 10.8 10.9 10.10 10.5.4 Port Pull-Up Control Register 6 (PUCR6)............................................................ 299 10.5.5 Port Drive Control Register 6 (PDVR6) ............................................................... 300 Port 8.................................................................................................................................. 301 10.6.1 Port Mode Register 8 (PMR8) ..............................................................................
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Section 11 Data Transfer Controller (DTC) ......................................................335 11.1 Features.............................................................................................................................. 335 11.2 Register Descriptions ......................................................................................................... 337 11.2.1 DTC Mode Register A (MRA) ............................................................................. 338 11.2.
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12.2.4 Event Link Option Setting Register B (ELOPB) .................................................. 377 12.2.5 Event Link Option Setting Register C (ELOPC) .................................................. 377 12.2.6 Port-Group Setting Registers 1 and 2 (PGR1 and PGR2)..................................... 378 12.2.7 Port-Group Control Registers 1 and 2 (PGC1 and PGC2).................................... 379 12.2.8 Port Buffer Registers 1 and 2 (PDBF1 and PDBF2)...........................................
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Section 14 Timer RB .........................................................................................419 14.1 Overview............................................................................................................................ 419 14.2 Register Descriptions ......................................................................................................... 420 14.2.1 Timer RB Control Register (TRBCR) .................................................................. 421 14.2.
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15.3 Operation ........................................................................................................................... 463 15.3.1 Timer Mode Operation ......................................................................................... 465 15.3.2 PWM Mode Operation.......................................................................................... 470 15.3.3 PWM2 Mode Operation........................................................................................ 475 15.3.
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16.3 Operation ........................................................................................................................... 536 16.3.1 Counter Operation ................................................................................................ 545 16.3.2 Waveform Output by Compare Match.................................................................. 548 16.3.3 Input Capture Function ......................................................................................... 551 16.3.
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Section 18 Timer RG.........................................................................................629 18.1 Features.............................................................................................................................. 629 18.2 Register Descriptions ......................................................................................................... 632 18.2.1 Timer RG Mode Register (TRGMDR)................................................................. 633 18.2.
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20.3 20.4 20.5 20.6 20.7 20.8 20.9 20.2.2 Receive Data Register (RDR)............................................................................... 683 20.2.3 Transmit Shift Register (TSR) .............................................................................. 683 20.2.4 Transmit Data Register (TDR).............................................................................. 684 20.2.5 Serial Mode Register (SMR) ................................................................................
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Section 21 I2C Bus Interface 2 (IIC2)................................................................729 21.1 Features.............................................................................................................................. 729 21.2 Register Descriptions ......................................................................................................... 732 21.2.1 IIC2/SSU Select Register (ICSUSR) .................................................................... 732 21.2.
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22.2.5 SS Mode Register 2 (SSMR2) .............................................................................. 774 22.2.6 SS Enable Register (SSER) .................................................................................. 777 22.2.7 SS Status Register (SSSR).................................................................................... 778 22.2.8 SS Receive Data Register (SSRDR) ..................................................................... 780 22.2.
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.3 Operation ........................................................................................................................... 832 24.4 A/D Conversion Mode Operation ...................................................................................... 833 24.4.1 Single Mode in A/D Conversion Mode ................................................................ 833 24.4.2 Scan Mode in A/D Conversion Mode................................................................... 835 24.
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26.3 Operation ........................................................................................................................... 868 26.3.1 Power-On Reset Function..................................................................................... 868 26.3.2 Low-Voltage Detection Circuit............................................................................. 869 Section 27 List of Registers ...............................................................................881 27.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 1 Overview Section 1 Overview 1.1 Features The H8S/Tiny series is a 16-bit CISC (complex instruction set computer) microcontroller, each member of the H8S/Tiny series has the powerful H8S/2000 CPU with an internal 32-bit architecture as its core. The H8S/2000 CPU provides upwards-compatibility with the other members of the Renesas H8 Family: H8/300, H8/300H Tiny and H8/300H.
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Section 1 Overview H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Classification Module/ Function Description CPU CPU • 16-bit high-speed H8S/2000 CPU (CISC type) Upwardly compatible with H8/300 and H8/300H CPUs at object level • General-register architecture (sixteen 16-bit general registers) • Eight addressing modes • 16-Mbyte address space ⎯ Program: 16 Mbytes available ⎯ Data: 16 Mbytes available Interrupt (source) • 65 basic instructions including bit operation
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Classification Module/ Function Description Voltage detection Low-voltage Voltage drop detected detection circuit (LVD) DMA Data transfer • controller • (DTC) A/D converter A/D converter (ADC) Section 1 Overview Transfer via any number of channels possible Three transfer modes • • • • 10-bit resolution × eight to sixteen input channels Sample and hold function included Conversion time: 2 μs per channel Two operating modes: s
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Section 1 Overview Classification H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Module/ Function 2 Serial interfaces I C bus interface 2 (IIC2) Description • • One channel (SSU and selection format) Continuous transmission and reception possible • Two transmission/reception formats ⎯ I C bus format: generates start and stop conditions in master mode automatically, acknowledge bit, master or slave operation 2 ⎯ Clock-synchronous serial format: no acknowledge bit, master oper
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Classification Module/ Function Packages Section 1 Overview Description • 64-pin QFP package (PLQP0064KB-A) ⎯ Former code: 64P6Q-A ⎯ Body size: 10 × 10 mm ⎯ Pin pitch: 0.50 mm • 64-pin QFP package (PLQP0064GA-A) ⎯ Former code: 64P6U-A ⎯ Body size: 14 × 14 mm ⎯ Pin pitch: 0.80 mm • 80-pin QFP package (PLQP0080JA-A) ⎯ Former code: FP-80W ⎯ Body size: 14 × 14 mm ⎯ Pin pitch: 0.
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Section 1 Overview 1.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group List of Products Table 1.2 lists products of this series, and figure 1.1 shows how to read the part number. Table 1.2 List of Products Group Part No.
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Section 1 Overview H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Group Part No.
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Section 1 Overview 1.
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Section 1 Overview H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group VCC VSS Port 2 Port 3 Peripheral data bus P20/SCK3 P21/RXD P22/TXD P23 P24/TRDOI_0 P25/SCK3_2 P26/RXD_2 P27/TXD_2 P30 P31 P32 P33 P34 P35/SCK3_3 P36/RXD_3 P37/TXD_3 P50/TCLKA P51/TCLKB P52/TGIOA P53/TGIOB P54/SSO P55/SSCK P56/SDA/SCS P57/SCL/SSI Low-voltage detection circuit Sub-clock oscillator X1 X2 ELC Low-speed OCO P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/IRQ5 P16/IRQ6 P17/IRQ7 Port 5 Main clo
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Section 1 Overview H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Sub-clock oscillator Port 1 X1 X2 Port 2 Main clock oscillator P20/SCK3 P21/RXD P22/TXD P23 P24/TRDOI_0 P25/SCK3_2 P26/RXD_2 P27/TXD_2 Port 3 PJ0/OSC1 PJ1/OSC2 Peripheral address bus DTC RAM Peripheral data bus Bus controller Internal address bus H8S/2000 CPU ROM Internal data bus RES TEST P10/IRQ0 P11/IRQ1 P12/IRQ2 P13/IRQ3 P14/IRQ4 P15/IRQ5 P16/IRQ6 P17/IRQ7 P30 P31 P32 P33 P34 P35/SCK3_3 P36/RXD
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Section 1 Overview H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Pin Assignments 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 49 32 50 31 51 30 52 29 53 28 H8S/20103 Group H8S/20115 Group PLQP0064KB-A 64P6Q-A/FP-64K PLQP0064GA-A 64P6U-A (top view) 54 55 56 57 58 59 60 27 26 25 24 23 22 21 16 15 14 13 12 11 9 10 8 P63/FTIOD0 P50/TCLKA P51/TCLKB P52/TGIOA P53/TGIOB P57/SCL/SSI P56/SDA/SCS P55/SSCK P54/SSO P17/IRQ7 P16/IRQ6 P15/IRQ5 P30/FTIOA P31/
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Section 1 Overview 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 61 40 62 39 63 38 64 37 65 36 66 35 67 34 H8S/20203 Group H8S/20215 Group PLQP0080JA-A FP-80W (top view) 68 69 70 71 72 33 32 31 30 29 20 19 18 17 16 15 14 13 12 P26/RXD_2 P27/TXD_2 P11/IRQ1 P10/IRQ0 P50/TCLKA P51/TCLKB P52/TGIOA P53/TGIOB P54/SSO P55/SSCK P56/SDA/SCS P57/SCL/SSI P17/IRQ7 P16/IRQ6 P15/IRQ5 P14/IRQ4 P30 P31 P32 P33 PB6/AN6/DA0 PB7/AN7/DA1 AVCC X2 X1 NC RES TEST Vss PJ1/OSC2
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Section 1 Overview 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 61 40 62 39 63 38 64 37 65 36 66 35 67 34 H8S/20223 Group H8S/20235 Group PLQP0080JA-A FP-80W (top view) 68 69 70 71 72 33 32 31 30 29 20 19 18 17 16 15 14 13 12 P26/RXD_2 P27/TXD_2 P11/IRQ1 P10/IRQ0 P50/TCLKA P51/TCLKB P52/TGIOA P53/TGIOB P54/SSO P55/SSCK P56/SDA/SCS P57/SCL/SSI P17/IRQ7 P16/IRQ6 P15/IRQ5 P14/IRQ4 P30 P31 P32 P33 PB6/AN6/DA0 PB7/AN7/DA1 AVCC X2 X1 NC RES TEST Vss PJ1/OSC2
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Section 1 Overview 1.4.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Pin Functions Table 1.3 Pin Functions Pin No. Classification Symbol H8S/20103 and H8S/20115 Groups H8S/20203, H8S/20223, H8S/20215, and H8S/20235 Groups I/O Power supply VCC 12 12 Input Power supply pin. Connect this pin to the system power supply. VSS 9 9, 50 Input Ground pin. Connect this pin to the system power supply (0 V).
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Section 1 Overview H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Pin No. Classification Symbol H8S/20103 and H8S/20115 Groups H8S/20203, H8S/20223, H8S/20215, and H8S/20235 Groups I/O Clock X1 5 5 X2 4 4 7 7 Input Reset pin. Applying a low level signal to this pin resets this LSI. TEST 8 8 Input Test pin. Connect this pin to VSS. NMI 35 13 Input Non-maskable interrupt request input pin. Be sure to pull up this pin with a resistor.
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Section 1 Overview H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Pin No. H8S/20103 and H8S/20115 Groups H8S/20203, H8S/20223, H8S/20215, and H8S/20235 Groups I/O TRGC 20 ⎯ Input Pin for external trigger input. TRCOI 47 ⎯ Input Pin for inputting the timeroutput enable or disable signal. FTIOA0 36 42 I/O Pin for output-compare output, input-capture input, and external clock input.
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Section 1 Overview H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Pin No. H8S/20103 and H8S/20115 Groups H8S/20203, H8S/20223, H8S/20215, and H8S/20235 Groups I/O FTIOA2 ⎯ 62 I/O Pin for output-compare output, input-capture input, and external clock input. FTIOB2 ⎯ 63 I/O Pin for output-compare output, input-capture input, and PWM output.
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Section 1 Overview H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Pin No. H8S/20103 and H8S/20115 Groups H8S/20203, H8S/20223, H8S/20215, and H8S/20235 Groups I/O Serial TXD communication TXD_2 interface 3 TXD_3 (SCI3) RXD 46 54 50 39 13 17 45 53 RXD_2 49 40 RXD_3 14 18 SCK3 44 52 SCK3_2 48 41 SCK3_3 15 19 SDA 26 SCL Classification Symbol I2C bus interface 2 (IIC2) Output Output pins for data transmission. Input Input pins for data reception.
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Section 1 Overview H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Pin No. H8S/20103 and H8S/20115 Groups Classification Symbol AD converter_1 AD 8 converter_2* DA converter 6 AN11 to AN0* 2, 1, 64, 63, 73 to 70, 2, 1 59 to 62 80 to 75 ADTRG1 * AN3_2 to AN0_2 Description Input Analog input pins. *7 Input Input pin for the conversion-start trigger signal. ⎯ 69 to 66 Input Analog input pins. ADTRG2 ⎯ *7 Input Input pin for the conversion-start trigger signal.
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Section 1 Overview H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Notes: 1. In the H8S/20103 and H8S/20115 Groups, the IRQ0 and IRQ4 pins are not available with the initial setting of the PMC. 2. The TRAO and TRGB pins are not available with the initial setting of the PMC. 3. The H8S/20203, H8S/20223, H8S/20215, and H8S/20235 Groups do not incorporate timer RC. 4. The TRDOI_1 pin is not available with the initial setting of the PMC. 5.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 2 CPU Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. 2.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • High-speed operation All frequently-used instructions are executed in one or two states ⎯ 8/16/32-bit register-register add/subtract: 1 state ⎯ 8 × 8-bit register-register multiply: 12 states (MULXU.B), 13 states (MULXS.B) ⎯ 16 ÷ 8-bit register-register divide: 12 states (DIVXU.B) ⎯ 16 × 16-bit register-register multiply: 20 states (MULXU.W), 21 states (MULXS.W) ⎯ 32 ÷ 16-bit register-register divide: 20 states (DIVXU.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 2.1.2 Section 2 CPU Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers Eight 16-bit extended registers, and one 8-bit and two 32-bit control registers, have been added. • Expanded address space Normal mode supports the same 64-Kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space.
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Section 2 CPU 2.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Note that this LSI supports only advanced mode. Advanced mode supports a maximum 16-Mbyte address space. 2.2.1 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H'00000000 Reserved Reset exception vector H'00000003 Reserved H'00000004 (Reserved for system use) H'00000007 H'00000008 Exception vector table (Reserved for system use) H'00000014 Reserved Exception vector 1 Figure 2.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • Stack structure In advanced mode, the program counter (PC) is pushed onto the stack in a subroutine call, and the PC and condition-code register (CCR) are pushed onto the stack in exception handling. They are stored as shown in figure 2.2. EXR is not pushed onto the stack in interrupt control mode 0. For details, see section 3, Exception Handling.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H8S/20103 H'000000 H8S/20102 H'000000 Interrupt vectors Interrupt vectors On-chip flash ROM (96 Kbytes) On-chip flash ROM (128 Kbytes) H'017FFF H'018000 H'01FFFF H'020000 Reserved area Reserved area H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 Kbytes) H'EFFFFF H'F00000 H'F01FFF H'F02000 Reserved area Data flash area (8 Kbytes) Reserved area H'FF0000 H'FF0000 On-chip I/O registers On-chip I/O regist
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H8S/20203 H'000000 H8S/20202 H'000000 Interrupt vectors Interrupt vectors On-chip flash ROM (96 Kbytes) On-chip flash ROM (128 Kbytes) H'017FFF H'018000 H'01FFFF H'020000 Reserved area Reserved area H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 Kbytes) H'EFFFFF H'F00000 H'F01FFF H'F02000 Reserved area Data flash area (8 Kbytes) Reserved area H'FF0000 H'FF0000 On-chip I/O registers On-chip I/O regist
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H8S/20223 H'000000 H8S/20222 H'000000 Interrupt vectors Interrupt vectors On-chip flash ROM (96 Kbytes) On-chip flash ROM (128 Kbytes) H'017FFF H'018000 H'01FFFF H'020000 Reserved area Reserved area H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 Kbytes) H'EFFFFF H'F00000 H'F01FFF H'F02000 Reserved area Data flash area (8 Kbytes) Reserved area H'FF0000 H'FF0000 On-chip I/O registers On-chip I/O regist
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H8S/20115 H'000000 H8S/20114 H'000000 Interrupt vectors Interrupt vectors On-chip flash ROM (192 Kbytes) On-chip flash ROM (256 Kbytes) H'02FFFF H'030000 H'03FFFF H'040000 Reserved area Reserved area H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 Kbytes) H'EFFFFF H'F00000 H'F01FFF H'F02000 Reserved area Data flash area (8 Kbytes) Reserved area H'FF0000 H'FF0000 On-chip I/O registers On-chip I/O regis
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H8S/20215 H'000000 H8S/20214 H'000000 Interrupt vectors Interrupt vectors On-chip flash ROM (192 Kbytes) On-chip flash ROM (256 Kbytes) H'02FFFF H'030000 H'03FFFF H'040000 Reserved area Reserved area H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 Kbytes) H'EFFFFF H'F00000 H'F01FFF H'F02000 Reserved area Data flash area (8 Kbytes) Reserved area H'FF0000 H'FF0000 On-chip I/O registers On-chip I/O regis
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H8S/20235 H'000000 H8S/20234 H'000000 Interrupt vectors Interrupt vectors On-chip flash ROM (192 Kbytes) On-chip flash ROM (256 Kbytes) H'02FFFF H'030000 H'03FFFF H'040000 Reserved area Reserved area H'EFFFFF H'F00000 H'F01FFF H'F02000 Data flash area (8 Kbytes) H'EFFFFF H'F00000 H'F01FFF H'F02000 Reserved area Data flash area (8 Kbytes) Reserved area H'FF0000 H'FF0000 On-chip I/O registers On-chip I/O regis
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.4. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8bit extended control register (EXR), and an 8-bit condition code register (CCR).
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Section 2 CPU 2.4.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.5 illustrates the usage of the general registers.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Free area SP (ER7) Stack area Figure 2.6 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.
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Section 2 CPU 2.4.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 2 CPU Bit Symbol Bit Name Description R/W 2 Z Zero flag [Setting condition] R/W When data is zero. [Clearing condition] When data is not zero. 1 V Overflow flag [Setting condition] R/W When an overflow occurs after an arithmetic instruction has been executed. [Clearing condition] When no overflow occurs after an arithmetic instruction has been executed.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • U (user bit) This bit can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. • N (negative bit) This bit stores the value of the most significant bit of data as a sign bit. • C (carry flag) This flag is set to 1 when a carry occurs, and cleared to 0 otherwise.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.7 shows the data formats of general registers.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Data Type Register Number Word data Rn Data Format 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn LSB Legend: ERn En Rn RnH RnL MSB LSB : General register ER : General register E : General register R : General register RH : General register RL : Most significant bit : Least significant bit Figure 2.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 2.5.2 Memory Data Formats Figure 2.8 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
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Section 2 CPU 2.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 2.6.1 Section 2 CPU Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
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Section 2 CPU Table 2.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Data Transfer Instructions Instruction 1 Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in this LSI. MOVTPE B Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 2.4 Section 2 CPU Arithmetic Operations Instructions (1) Instruction Size* Function ADD B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd SUB Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.
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Section 2 CPU Table 2.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Arithmetic Operations Instructions (2) Instruction 1 Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16bit quotient and 16-bit remainder.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 2.5 Section 2 CPU Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
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Section 2 CPU Table 2.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Shift Instructions Instruction Size* Function SHAL B/W/L Rd (shift) → Rd SHAR Performs an arithmetic shift on data in a general register. 1-bit or 2 bit shift is possible. SHLL B/W/L SHLR Performs a logical shift on data in a general register. 1-bit or 2 bit shift is possible. ROTL B/W/L ROTR Rd (rotate) → Rd Rotates data in a general register. 1-bit or 2 bit rotation is possible.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 2.7 Section 2 CPU Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0.
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Section 2 CPU Table 2.7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ∼ (
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 2.8 Branch Instructions Instruction Size Function Bcc ⎯ Branches to a specified address if a specified condition is true. The branching conditions are listed below.
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Section 2 CPU Table 2.9 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group System Control Instructions Instruction Size* Function TRAPA ⎯ Starts trap-instruction exception handling. RTE ⎯ Returns from an exception-handling routine. SLEEP ⎯ Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 2 CPU Table 2.10 Block Data Transfer Instructions Instruction Size Function EEPMOV.B ⎯ if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next: EEPMOV.W ⎯ if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next: Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc. Figure 2.9 Instruction Formats (Examples) Page 54 of 982 REJ09B0465-0300 Rev. 3.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
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Section 2 CPU 2.7.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 2.12 Absolute Address Access Ranges Absolute Address Data address Program instruction address 2.7.
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Section 2 CPU 2.7.8 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'000000 to H'0000FF in advanced mode).
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. Table 2.13 Effective Address Calculation No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct (Rn) rm Operand is general register contents.
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Section 2 CPU No 5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op @aa:16 31 op 0 H'FFFF 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 24 23 Don't care abs 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 2.8 Section 2 CPU Processing States The H8S/2000 CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and program stop state. Figure 2.11 indicates the state transitions. • Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state.
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Section 2 CPU H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 2. If the CPU is in sleep mode at the time of the request, bus mastership is transferred immediately.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 2.9 Usage Notes 2.9.1 TAS Instruction Section 2 CPU Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The H8S and H8/300 Series C/C++ Compiler of Renesas Electronics Corp. does not generate a TAS instruction. Accordingly, when a TAS instruction is used as a user-defined embedded function, register ER0, ER1, ER4, or ER5 should be used. 2.9.
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Section 2 CPU 2.9.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group EEPMOV Instruction 1. The EEPMOV instruction performs a block transfer. As shown in the following figure, EEPMOV transfers data whose start address is indicated by R5 for the number of bytes indicated by R4L to the address indicated by R6. R5 R6 R5 + R4L R6 + R4L 2.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 3 Exception Handling Section 3 Exception Handling 3.1 Exception Handling Types and Priority As table 3.1 indicates, exception handling is caused by a reset, trace, NMI interrupt, trap instruction, or interrupt. Exception handling is prioritized as shown in table 3.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
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Section 3 Exception Handling 3.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Reset A reset has the highest exception handling priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for the specified time at power-on and during operation, hold the RES pin low for the specified time.
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Section 3 Exception Handling H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (1) Reset Source Flag Register (RSTFR) Address: H'FF0620 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ SWRST PRST LVD2RST LVD1RST PORRST WRST 0 0 (0) (0) (0) (0) (0) (0) Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is read as 0. The write value should be 0.
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Section 3 Exception Handling (2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Reset Control Register (RSTCR) Address: H'FF06DA Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 WI WE ⎯ ⎯ ⎯ ⎯ ⎯ SRST 1 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 WI Write inhibit 0: Writing is permitted. W 1: Writing is inhibited. 6 WE Write enable 0: Writing is disabled. R/W 1: Writing is enabled.
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Section 3 Exception Handling H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 3.3.2 Reset Exception Handling When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, VOFR is cleared to H'0000, the T bit in EXR is cleared to 0, and the I bit in EXR and CCR is set to 1. 2.
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Section 3 Exception Handling 3.3.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupts immediately after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
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Section 3 Exception Handling H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 3.4 Trace Exception Handling Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 4, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction.
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Section 3 Exception Handling 3.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to four priority/mask levels to enable multiplexed interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product.
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Section 3 Exception Handling H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 3.4 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 1 ⎯ ⎯ ⎯ 2 1 ⎯ ⎯ 0 [Legend] 1: Set to 1 0: Cleared to 0 ⎯: Retains value prior to execution. 3.7 Stack Status after Exception Handling Figure 3.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling.
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Section 3 Exception Handling 3.8 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 4 Interrupt Controller Section 4 Interrupt Controller 4.1 Features • Two interrupt control modes Either of the two interrupt control modes can be selected by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Four priority levels can be set for each module for all interrupts except NMI.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group A block diagram of the interrupt controller is shown in figure 4.1. CPU INTM1 INTM0 INTCR NMIEG NMI input NMI input unit IRQ input IRQ input unit ISR Interrupt request Vector number ISCR IER Priority determination Internal interrupt sources IAD to ITGUD I I1 to I0 CCR EXR IPR Interrupt controller Figure 4.1 Block Diagram of Interrupt Controller Table 4.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 4.
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Section 4 Interrupt Controller 4.2.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupt Control Register (INTCR) Address: H'FF0520 Bit: b7 b6 ⎯ ⎯ 0 0 Value after reset: b5 b4 INTM[1:0] 0 b3 b2 b1 b0 NMIEG ADTRG1 ADTRG0 ⎯ 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved These bits are read as 0. The write value should be 0.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • ADTRG1 and ADTRG0 bits (ADTRG2 and ADTRG1 edge select) These bits select the input edge for the ADTRG2 and ADTRG1 pins. 4.2.
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Section 4 Interrupt Controller Table 4.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 4.2.3 IRQ Enable Register (IER) Address: H'FF0521 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 IRQ7E IRQ7 enable 0: IRQ7 interrupts are disabled. R/W 1: IRQ7 interrupts are enabled. 6 IRQ6E IRQ6 enable 0: IRQ6 interrupts are disabled.
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Section 4 Interrupt Controller 4.2.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol 3 [IRQ5SCB : IRQ5 sense IRQ5SCA] control B and A 2 Bit Name Section 4 Interrupt Controller Description R/W 00: Reserved (setting prohibited) R/W 01: Interrupt request is generated at falling edge of IRQ5 input. 10: Interrupt request is generated at rising edge of IRQ5 input. 11: Interrupt request is generated at both falling and rising edges of IRQ5 input.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • ISCRL Bit Symbol 7 [IRQ3SCB : IRQ3 sense IRQ3SCA] control B and A 6 Bit Name Description R/W 00: Reserved (setting prohibited) R/W 01: Interrupt request is generated at falling edge of IRQ3 input. 10: Interrupt request is generated at rising edge of IRQ3 input. 11: Interrupt request is generated at both falling and rising edges of IRQ3 input.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 4.2.
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Section 4 Interrupt Controller 4.2.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group IRQ Noise Canceler Control Register (INCCR) Address: H'FF0525 Bit: Value after reset: b7 b6 ⎯ ⎯ 0 0 b5 b4 b3 INCCR[5:4] 1 b2 b1 INCCR[3:2] 1 1 b0 INCCR[1:0] 1 1 1 Bit Bit Name Initial Value Description R/W 7 ⎯ Reserved These bits are always read as 0. The write value should always be 0.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 4.2.
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Section 4 Interrupt Controller 4.2.8 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Event Link Interrupt Control Status Register (ELCSR) Address: H'FF0528 Bit: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ ELIE2 ELIE1 ELF2 ELF1 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 to 4 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯ 3 ELIE2 ELC interrupt 2 0: ELF2 interrupts are disabled.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 4.3 Interrupt Sources 4.3.1 External Interrupt sources Section 4 Interrupt Controller There are nine external interrupts: NMI and IRQ7 to IRQ0. These external interrupts can be used to cause the device to exit from standby mode.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group IRQnE INCCRn IRQnSCB, IRQnSCA IRQnF Noise cancel circuit Edge detection circuit S IRQn interrupt request Q R IRQn input n = 7 to 0 Clear signal Figure 4.2 Block Diagram of IRQ7 to IRQ0 Interrupt 4.3.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 4.4 Section 4 Interrupt Controller Interrupt Exception Handling Vector Table Table 4.3 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. When interrupt control mode 2 is set, priorities among modules can be changed by the IPR. Modules set at the same priority will conform to their default priorities.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 4.3 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source Interrupt Source Vector 1 Number Vector Address* DTCER IPR Priority RES Pin Reset 0 H'0000 to H'0003 ⎯ ⎯ High WDT 1. RES pin reset LVD 2. WDT overflow 3. LVD reset 4.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Origin of Interrupt Source Interrupt Source Vector 1 Number Vector Address* DTCER IPR Priority IRQ0 22 H'0058 to H'005B DTCEA7 IPRB7 and IPRB6 High IRQ1 23 H'005C to H'005F DTCEA6 IPRB5 and IPRB4 IRQ2 24 H'0060 to H'0063 DTCEA5 IPRB3 and IPRB2 IRQ3 25 H'0064 to H'0067 DTCEA4 IPRB1 and IPRB0 IRQ4 26 H'0068 to H'006B DTCEA3 IPRC7 and IPRC6 IRQ5 27 H'006C to H'006F DTCEA2
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Section 4 Interrupt Controller Origin of Interrupt Source Interrupt Source Vector 1 Number Vector Address* DTCER IPR 37 H'0094 to H'0097 ⎯ IPRE7 and High IPRE6 SCI3_1 RXI 38 H'0098 to H'009B DTCEB1 SCI3_1 TXI 39 H'009C to H'009F DTCEB0 SCI3_1 TEI 40 H'00A0 to H'00A3 ⎯ 41 H'00A4 to H'00A7 ⎯ 42 H'00A8 to H'00AB DTCEC7 SCI3_1 ERI SCI3 channel 1 1. Overrun error 2. Parity error 3. Framing error SCI3 SCI3_2 ERI channel 2 1. Overrun error 2. Parity error 3.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Origin of Interrupt Source Interrupt Source Vector 1 Number Vector Address* DTCER ⎯ Reserved 63 to 68 H'00FC to H'0113 Timer RA/ HW-LIN 1.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Origin of Interrupt Source Interrupt Source Timer RD unit 0 channel 0 ITDMC0_0 (input capture C/compare match C) 78 H'0138 to H'013B DTCEE5 ITCMD0_0 (input capture D/compare match D) 79 H'013C to H'013F DTCEE4 ITDOV0_0 overflow Timer RD unit 0 channel 1 Vector Number Vector Address*1 DTCER 80 H'0140 to H'0143 ⎯ ITDUD0_0 underflow 81 H'0144 to H'0147 ⎯ ITDMA0_1 (input capture A/compare m
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Origin of Interrupt Source Interrupt Source Vector 1 Number Vector Address* DTCER IPR Priority Timer RD ITDMA1_3 (input unit 1 capture A/compare 4 channel 3* match A) 93 H'0174 to H'0177 ITDMB1_3 (input capture B/compare match B) 94 H'0178 to H'017B DTCEE2 ITDMC1_3 (input capture C/compare match C) 95 H'017C to H'017F DTCEE1 ITCMD1_3 (input capture D/compare match D) 96 H'0180 to H'0183 D
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Section 4 Interrupt Controller 4.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 4.4 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 4.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Program execution status No Interrupt generated Yes Yes NMI No Yes IFMBSYA* No I=0 No Retained Yes No IRQ0 Yes No IRQ1 Yes ITGUD Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Note: * Access interrupt when flash memory busy. Figure 4.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 REJ09B0465-0300 Rev. 3.
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Section 4 Interrupt Controller 4.5.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupt Control Mode 2 In interrupt control mode 2, mask control is executed in four levels for interrupt requests except NMI by comparing the EXR interrupt mask level (I1 and I0 bits*) in the CPU and the IPR setting. Figure 4.4 shows a flowchart of the interrupt acceptance operation. 1.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Program execution status Interrupt generated No Yes Yes NMI No Yes IFMBSYA* No Level 3 interrupt No Yes Mask level 2 or below Yes Level 2 interrupt No No Yes Level 1 interrupt Mask level 1 or below No No Yes Yes Mask level 0 No Yes Save PC, CCR, and EXR Retained Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Note: * Access interrupt whe
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Section 4 Interrupt Controller 4.5.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupt Exception Handling Sequence Figure 4.5 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0, the program area, and stack area are in on-chip memory. Page 102 of 982 REJ09B0465-0300 Rev. 3.
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REJ09B0465-0300 Rev. 3.00 Sep 17, 2010 (1) (2) (4) (3) Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
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Section 4 Interrupt Controller 4.5.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupt Response Time Table 4.5 shows interrupt response time, the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. Table 4.5 Interrupt Response Times Interrupt Control Mode 0 Interrupt Control Mode 2 No.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 4.6 Usage Notes 4.6.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to mask interrupt requests, the masking becomes effective after execution of the instruction.
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Section 4 Interrupt Controller 4.6.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid after two states that execution of the instruction ends. 4.6.
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Section 4 Interrupt Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 4.6.5 Changing PMR, ISCRH, ISCRL and INCCR When the PMR, ISCRH, ISCRL, and INCCR are modified to change an IRQ7 to IRQ0 interrupt function, the interrupt request flag bit may be set to 1 at an unintended time. To prevent this, the pin function should be changed when the interrupt request is disabled, then the interrupt request flag should be cleared to 0 after a specific interval time*. Figure 4.
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Section 4 Interrupt Controller 4.6.7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group NMI Pin The NMI pin is also used to set up entry to boot mode on exit from the reset state. In using the NMI pin, note that the low-level should not be being applied to the NMI pins on exit from the reset state (including power-on reset). In general, it is recommended that the connection of a pullup resistor to the NMI pin. Page 108 of 982 REJ09B0465-0300 Rev. 3.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 5 Clock Pulse Generator The clock pulse generator is comprised of the main oscillator, a duty correction circuit, a lowspeed OCO (OCO: on-chip oscillator), a sub-oscillator, a clock selection circuit, a system clock divider, a PSC divider for peripheral modules, and a φs divider for the bus master and memory. Table 5.1 lists clock source symbols and their meanings used in this manual. Table 5.
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Section 5 Clock Pulse Generator 5.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Overview • Choice of three clock sources: φloco, φsub, and φosc • Main oscillation backup function By detecting a φosc stop, it is possible to automatically switch the system clock to φlow. • Clock switching interrupt function When the system clock is switched from φosc to φloco, a CPU interrupt can be generated if enabled. Figure 5.1 shows a block diagram of the clock pulse generation circuit.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 5 Clock Pulse Generator The system reference clock (φbase) is the basic clock on which the CPU and on-chip peripheral modules operate. φbase can be divided by a value from 1 to 128 in the system clock divider, and the divided clock is supplied as the system clock φ. The system clock φ is divided by a value from 2 to 8192 in the PSC divider, and the divided clock can be supplied to on-chip peripheral modules.
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Section 5 Clock Pulse Generator 5.2.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Backup Control Register (BAKCR) Address: H'FF06D4 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 WI WE OSCBAKE BAKCKSEL CKSWIE CKSWIF OSCHLT ⎯ 1 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 WI Write inhibit 0: Writing is permitted. W 1: Writing is inhibited. 6 WE Write enable 0: Writing is disabled. R/W 1: Writing is enabled.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 5 Clock Pulse Generator Bit Symbol Bit Name Description 1 OSCHLT Main oscillator 0: The external main oscillator is oscillating. stop detect flag 1: The external main oscillator is stopped. R/W R [Setting condition] When the external main oscillator is stopped while OSCBAKE is 1. 0 ⎯ Reserved This bit is read as 0. The write value should be 0.
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Section 5 Clock Pulse Generator 5.2.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group System Clock Control Register (SYSCCR) Address: H'FF06D0 Bit: Value after reset: b7 b6 b5 b4 b3 WI WE PHIHSEL PHILSEL ⎯ 1 0 0 0 0 b2 b1 SUBNC[1:0] 0 0 b0 ⎯ 0 Bit Symbol Bit Name Description R/W 7 WI Write inhibit 0: Writing is permitted. W 6 WE Write enable 1: Writing is inhibited. R/W 0: Writing is disabled. 1: Writing is enabled.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 5 Clock Pulse Generator Bit Symbol Bit Name Description R/W 2, 1 SUBNC [1:0]* φsub noise canceler sampling function setting 00: The sampling circuit is disabled. R/W Reserved This bit is read as 0. The write value should be 0. ⎯ 0 Notes: 01: Sampling is performed at φbase/4. 10: Sampling is performed at φbase/16. 11: Setting prohibited ⎯ A MOV instruction should be used to write to this register.
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Section 5 Clock Pulse Generator 5.2.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Power-Down Control Register 1 (LPCR1) Address: H'FF06D1 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 WI WE SSBY PSCSTP SLEEPRS STBYRS ⎯ PHIBSEL 1 0 0 1 0 0 0 0 Bit Symbol Bit Name Description R/W 7 WI Write inhibit 0: Writing is permitted. W 1: Writing is inhibited. 6 WE Write enable 0: Writing is disabled. R/W 1: Writing is enabled.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 5 Clock Pulse Generator Bit Symbol Bit Name Description R/W 0 PHIBSEL φbase clock source select 0: φlow R/W 1: φhigh [Setting conditions] • When 1 is written to this bit. • When the system returns from sleep mode while SLEEPRS is 1. • When the system returns from standby mode while STBYRS is 1. [Clearing conditions] • When 0 is written to this bit.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • STBYRS bit (φ source select for recovery from standby mode) Selects a clock source to be used when a transition is made from standby mode to active mode. • PHIBSEL bit (φbase clock source select) Selects a clock source for the φbase to be used in active mode or sleep mode. 5.2.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • WI (write inhibit) This register can be written to only when this bit is 0. This bit is always read as 1. • WE bit (write enable) Bits 2 to 0 in this register can be written to when this bit is 1. • PHI2 bit to PHI0 bit (system clock φ select) Selects a clock source for the system clock φ to be used in active mode or sleep mode. The clock is changed immediately after this bit is set. 5.2.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 4 SLEEPINT Sleep mode 0: No interrupt has occurred in sleep mode. interrupt 1: An interrupt has occurred in sleep mode. generation flag [Setting condition] R When an interrupt is generated in sleep mode. [Clearing condition] When an interrupt is generated in states other than sleep mode.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 5.2.6 OSC Oscillation Settling Control Status Register (OSCCSR) Address: H'FF06D5 Bit: b7 b6 b5 b4 OSCWEF ⎯ ⎯ ⎯ 0 0 0 0 Value after reset: Bit Name b3 b2 b1 b0 1 1 STS[3:0] 1 1 Bit Symbol Description R/W 7 OSCWEF φosc oscillation 0: Number of wait states for a stable φosc oscillation settling wait has not elapsed.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group If the φosc is already oscillating stably or the φosc is an external clock input, wait time can be selected from 16 states (STS[3:0]=B'0000). Table 5.2 Relationship between Operation Frequency and Number of Wait States Bit Operation Frequency STS3 STS2 STS1 STS0 Number of Wait States 0 0 0 0 16 states 0.00 0.00 0.00 0.00 0.00 0 0 0 1 32 states 0.00 0.00 0.00 0.00 0.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 5.3 Section 5 Clock Pulse Generator Operation of Selection of System Reference Clock After a reset, this LSI enters active mode operating in low-speed clocks. The user, by means of software, can change the system reference clock from a low-speed OCO clock to the main oscillator clock or a sub-oscillator clock. Figure 5.2 shows a transition diagram between system reference clock states. Table 5.
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Section 5 Clock Pulse Generator Table 5.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Clock Source Switching Bit PHIBSEL PHIHSEL PHILSEL Switching Operation 0 Don't care 0→1 φloco → φsub 0 Don't care 1→0 φsub → φloco 0→1 1 0 φloco → φosc 1→0 1 0 φosc → φloco 0→1 1 1 φsub → φosc 1→0 1 1 φosc → φsub Page 124 of 982 REJ09B0465-0300 Rev. 3.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 5.4 shows the low-speed OCO, main oscillator, and sub-oscillator operation states in each operating mode (system state). Table 5.
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Section 5 Clock Pulse Generator 5.3.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Switching System Reference Clock to φosc Figure 5.3 shows a flowchart of the process in which the system reference clock is switched from φloco to φosc. The LSI operates at the low-speed OCO clock. [1] Set at least 6.5 ms of oscillation settling time according to the oscillation frequency. Start Set oscillation settling time with STS[3:0] in OSCCSR.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group The LSI operates at the low-speed OCO clock. Start Set oscillation settling time with STS[3:0] in OSCCSR. [1] Set as least 6.5 ms of oscillation settling time according to the oscillation frequency. [1] [2] Select the oscillator functions for PJ0 and PJ1 pins. Set PMRJ[1:0] in PMRJ. [2] Wait for stable oscillation by polling OSCWEF in OSCCSR. [3] Set PHIHSEL in SYSCCR to 1.
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Section 5 Clock Pulse Generator 5.3.2 (1) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Clock Change Timing Switching Division Ratio for the Same Clock Source Figure 5.5 shows a division ratio switching timing chart for the same clock source. φbase PHI[2:0] 000 (divided by 1) 010 (divided by 4) 001 (divided by 2) φ Figure 5.5 Timing of Division Ratio Switching for the Same Clock Source Page 128 of 982 REJ09B0465-0300 Rev. 3.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) Switching System Reference Clock Source Figures 5.6 and 5.7 show clock source switching timing charts for the system reference clock.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group CLKA CLKB SELA SELB φbase Operation at CLKA Oscillation settling wait time Operation at CLKB [Legend] CLKA: Clock A CLKB: Clock B SELA: CLKA select signal SELB: CLKB select signal φbase: System base clock Note: The oscillation settling time differs according to the clock source. Figure 5.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 5.3.3 Backup Operation If the operating clock for the system is φosc and the backup function is enabled, when the main oscillator detects an oscillation halt condition, the system clock automatically switches to φlow, according to BAKCKSEL in BAKCR.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group φOSC OSCHLT BAKCLK φbase Operation at main oscillator clock φOSC stops Clock switching time Operation at backup destination clock [Legend] φOSC: Main oscillator clock OSCHLT: Main oscillator clock stop detection signal BAKCLK: Backup destination clock φbase: System base clock Figure 5.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group φOSC OSCHLT BAKCLK φbase Operation at main oscillator clock φOSC stops. Oscillation settling time Clock switching time Operation at backup destination clock [Legend] φOSC: Main oscillator clock OSCHLT: Main oscillator clock stop detection signal BAKCLK: Backup destination clock φbase: System base clock Figure 5.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group φOSC OSCHLT BAKCLK φbase Operation at main oscillator clock φOSC stops. Oscillation settling time Clock switching time Operation at backup destination clock [Legend] φOSC: Main oscillator clock OSCHLT: Main oscillator clock stop detection signal BAKCLK: Backup destination clock φbase: System base clock Figure 5.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 5.4 Main Clock Oscillator This LSI has two methods to supply external clock pulses into it: connecting a crystal or ceramic resonator, and an external clock. For setting PJ0/OSC1 and PJ1/OSC2/CLKOUT for a crystal resonator or an external clock, see section 10.10.1, Port Mode Register J (PMRJ). Figure 5.12 shows a block diagram of the Main clock oscillator.
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Section 5 Clock Pulse Generator 5.4.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Connecting Ceramic Resonator Figure 5.14 shows an example of connecting a ceramic resonator. A damping resistor Rd should be added, if necessary. Since the resistor values vary depending on the resonator, use values recommended by the resonator manufacturer. C1 PJ0/OSC1 C2 PJ1/OSC2/CLKOUT C1 = C2 = 5 to 30 pF Rd Figure 5.14 Example of Connection to Ceramic Resonator 5.4.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 5.5 Subclock Oscillator Figure 5.16 shows a block diagram of the subclock oscillator. X2 X1 Figure 5.16 Block Diagram of Subclock Oscillator 5.5.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.17. A damping resistor Rd should be added, if necessary.
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Section 5 Clock Pulse Generator 5.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Prescaler The prescaler is a 13-bit counter using the system clock (φ) as its input clock. The outputs, which are divided clocks, are used as internal clocks by the on-chip peripheral modules. The prescaler is initialized to H'0000 and stops counting after a reset. It starts counting when the PSCSTP bit in LPCR1 is cleared. The prescaler counter cannot be accessed by the CPU.
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Section 5 Clock Pulse Generator H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 5.7 Usage Notes 5.7.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit parameters will differ depending on the resonator element, stray capacitance of the PCB, and other factors.
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Section 5 Clock Pulse Generator Page 140 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300 Rev. 3.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 6 Power-Down Modes Section 6 Power-Down Modes In addition to normal active mode, this LSI can enter either of the two power-down modes after release from a reset, in which power consumption is reduced.
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Section 6 Power-Down Modes 6.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Descriptions The registers related to power-down modes are listed below. • • • • • • Power-down control register 1 (LPCR1) Power-down control register 2 (LPCR2) Power-down control register 3 (LPCR3) Module standby control register 1 (MSTCR1) Module standby control register 2 (MSTCR2) Module standby control register 3 (MSTCR3) 6.1.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 6 Power-Down Modes Bit Symbol Bit Name Description R/W 2 MSTDTC DTC module standby 0: Operating state R/W Reserved These bits are read as 0. The write value should be 0. ⎯ 1, 0 Note: ⎯ * 1: Standby state When a peripheral module is in the module standby state, the registers of the module cannot be accessed. • MSTWDT bit (watchdog timer module standby) When this bit is set to 1, the WDT enters the standby state.
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Section 6 Power-Down Modes 6.1.
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Section 6 Power-Down Modes H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 6.1.
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Section 6 Power-Down Modes H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • MSTTMRA bit (timer RA module standby) When this bit is set to 1, timer RA enters the standby state. • MSTTMRB bit (timer RB module standby) When this bit is set to 1, timer RB enters the standby state. • MSTTMRC bit (timer RC module standby) When this bit is set to 1, timer RC enters the standby state.
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Section 6 Power-Down Modes H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among the operating modes. SLEEP instructions are used to cause a transition from the program execution state to the program halt state. Interrupts are used to return from the program halt state to the program execution state.
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Section 6 Power-Down Modes H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 6.1 shows the internal states of the LSI in each mode. Table 6.
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Section 6 Power-Down Modes H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group LPCR1 PSCSTP = 0 Function Peripheral modules IIC2/SSU LPCR1 PSCSTP = 1 Active Mode Sleep Mode Active Mode Sleep Mode Standby Mode Functioning Functioning Retained Retained Reset 4 4 Functioning Functioning Retained* Retained* Reset D/A converter Functioning Functioning Functioning Functioning Reset A/D converter_1, A/D converter_2 Notes: 1.
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Section 6 Power-Down Modes 6.2.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Standby Mode When a SLEEP instruction is executed in active mode with the SSBY bit = 1 in LPCR1, a transition to standby mode is made. In standby mode, clock oscillation is stopped and thus the CPU, DTC, and all the on-chip peripheral modules (except timer RE and WDT) are stopped.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 6.4 Section 6 Power-Down Modes Module Standby Function The module standby function is available for any peripheral module. When a module is set to the module standby state, the clock supply to the module stops placing the module in the power-down state. Setting the corresponding bit to the module in MSTCR to 1 places the module in the module standby state and clearing the bit cancels the module standby state.
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Section 6 Power-Down Modes Page 152 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300 Rev. 3.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 7 ROM Section 7 ROM The features of the on-chip flash memory are described below. 7.1 Overview • Programming/erasing method Four bytes are programmed simultaneously. A single block is erased at a time; only one block should be erased at a time even when the entire ROM area is to be erased. • Programming/erasing time Programmable ROM programming time: 150 μs (typ.) for 4-byte simultaneous programming, i.e., 38 μs (typ.
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Section 7 ROM 7.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Block Configuration Figure 7.1 shows the blocks of the flash memory. The user ROM area contains the programmable ROM area for storing the microcomputer's operating program and the data flash area for storing data. In the figure, the thick-line frames each indicate an erasure block (erasing unit); the thin-line frames each indicate a programming unit. The values in the frames are addresses.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H8S/20103, H8S/20203, and H8S/20223 (programmable ROM: 128 Kbytes, data flash: 8 Kbytes) Programming unit: 4 bytes Programmable ROM block 0 (erasing unit: 16 Kbytes) Programmable ROM block 1 (erasing unit: 32 Kbytes) Programmable ROM block 2 (erasing unit: 32 Kbytes) Programmable ROM block 3 (erasing unit: 32 Kbytes) Programmable ROM block 4 (erasing unit: 16 Kbytes) Data flash A block 5 (erasing unit: 4 Kbytes) Dat
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H8S/20102, H8S/20202, and H8S/20222 (programmable ROM: 96 Kbytes, data flash: 8 Kbytes) Programming unit: 4 bytes Programmable ROM block 0 (erasing unit: 16 Kbytes) Programmable ROM block 1 (erasing unit: 32 Kbytes) Programmable ROM block 2 (erasing unit: 32 Kbytes) Programmable ROM block 3 (erasing unit: 16 Kbytes) Data flash A block 5 (erasing unit: 4 Kbytes) Data flash B block 6 (erasing unit: 4 Kbytes) H'000000
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H8S/20115, H8S/20215, and H8S/20235 (programmable ROM: 256 Kbytes, data flash: 8 Kbytes) Programming unit: 4 bytes Programmable ROM block 0 (erasing unit: 16 Kbytes) Programmable ROM block 1 (erasing unit: 64 Kbytes) Programmable ROM block 2 (erasing unit: 64 Kbytes) Programmable ROM block 3 (erasing unit: 64 Kbytes) Programmable ROM block 4 (erasing unit: 48 Kbytes) Data flash A block 5 (erasing unit: 4 Kbytes) Dat
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H8S/20114, H8S/20214, and H8S/20234 (programmable ROM: 192 Kbytes, data flash: 8 Kbytes) Programming unit: 4 bytes Programmable ROM block 0 (erasing unit: 16 Kbytes) Programmable ROM block 1 (erasing unit: 64 Kbytes) Programmable ROM block 2 (erasing unit: 64 Kbytes) Programmable ROM block 3 (erasing unit: 48 Kbytes) Data flash A block 5 (erasing unit: 4 Kbytes) Data flash B block 6 (erasing unit: 4 Kbytes) H'000000
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 7.3 CPU Reprogramming Mode In CPU reprogramming mode, the user ROM area can be reprogrammed by executing the software commands by the CPU. The software commands should be issued to the specific area to be reprogrammed in the user ROM area. If an interrupt is requested during erasure operation in CPU reprogramming mode, erasure can be suspended to process the interrupt. This is referred to as erase-suspend function.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Item EW0 Mode EW1 Mode CPU state during autoprogramming and auto-erasure Operating state Hold state (I/O ports retain the states in which they have been before the command is executed.) Flash memory state detection Read the FMPRSF, FMERSF, and FMEBSF bits in FLMSTR in a program.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 7.3.1 Section 7 ROM EW0 Mode EW0 mode can be selected by transferring the reprogramming-control program to the RAM, branching to the program in the RAM, setting the FMEWMOD bit in FLMCR1 to 0, and setting the FMCMDEN bit in FLMCR1 to 1 (to enable software commands), in this order. Programming and erasure operations can be controlled through software commands.
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Section 7 ROM 7.4 • • • • H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Descriptions Flash memory control register 1 (FLMCR1) Flash memory control register 2 (FLMCR2) Flash memory data flash protect register (DFPR) Flash memory status register (FLMSTR) 7.4.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • FMLBD bit (lock bit disable) This bit disables the lock-bit function. Setting FMLBD to 1 enables erasing/programming the block to which the lock-bit protection is applied. For the relationship between the FMLBD bit and the lock bit for the block, see table 7.2 below. Command sequence error occurs when the erasing/programming command is executed while disabling the erase program. Table 7.
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Section 7 ROM 7.4.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Flash Memory Control Register 2 (FLMCR2) Address: H'FF0661 Bit: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ FMRDYIE FMBSYRDIE FMISPE FMSPREQ FMSPEN 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7, 6 ⎯ Reserved ⎯ 5 ⎯ Reserved These bits are read as 0. The write value should be 0. 4 FMRDYIE *1*2 Flash read-ready interrupt enable 0: The ready interrupt is disabled.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 7 ROM FLMCR2 enables/disables flash memory interrupts, enables/controls a transition to erase-suspend mode. • FMRDYIE bit (flash read-ready interrupt enable) Setting the FMRDYIE bit to 1 enables an interrupt to be generated when the flash memory changes from the busy state to the ready state.
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Section 7 ROM 7.4.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Flash Memory Data Flash Protect Register (DFPR) Address: H'FF0662 Bit: Value after reset: Bit b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DFPR1 DFPR0 0 0 0 0 0 0 0 0 Bit Name Description R/W 7 to 2 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯ 1 Data flash B E/W disable*1*2 0: E/W of data flash B is enabled.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 7.4.4 Flash Memory Status Register (FLMSTR) Address: H'FF0663 Bit: b7 b6 b5 b4 b3 b2 b1 b0 FMRDYIF FMBSYRDIF FMEBSF FMERSF FMPRSF ⎯ ⎯ FMRDY 0 0 0 0 0 0 1 1 Value after reset: Bit Symbol Bit Name Description R/W 7 FMRDYIF *1*2*3 Flash readready interrupt request flag 0: The flash read-ready interrupt is not being requested. R/W 1: The flash read-ready interrupt is being requested.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 4 FMERSF Erase-suspend 0: Erase-suspend function is not being used. flag 1: Erase-suspend function is being used. R [Setting condition] • Erase-suspend mode is being used. [Clearing condition] • 3 FMPRSF *3*5 Programming status flag Erase-suspend mode is not being used.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 7 ROM • FMRDYIF (flash read-ready interrupt request flag) The FMRDYIF bit indicates that the flash memory has changed from the busy state to the ready state. When the FMRDYIF bit is set to 1 while the FMRDYIE bit is 1, an interrupt request is generated. • FMBSYRDIF (flash busy-read interrupt request flag) The FMBSYRDIF bit indicates that the user ROM area is accessed while the flash memory is in the busy state.
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Section 7 ROM 7.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group On-Board Programming The flash memory can be programmed/erased on board (boot mode and user mode), or by using a PROM programmer (programmer mode). When the reset is released, this LSI enters one of these modes depending on the levels of the signals input on the TEST, NMI, and ports, as shown in table 7.3. The levels of these signals must be fixed at least 80 μs before the reset is released.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group This LSI On-chip control-command analysis execution software Flash memory Host Control commands and programming data Programming tool and programming data RxD (P21) SCI On-chip RAM TxD (P22) Returned response Figure 7.
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Section 7 ROM Table 7.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Automatically Adjustable Bit Rates for the Host Host Bit Rate 9600 bps 4800 bps 2400 bps Note: Automatic adjustment of the SCI bit rate to 9600 bps will not be possible in some cases. If the signal indicating completion of bit-rate adjustment is not transmitted, restart the LSI in boot mode after reducing the bit rate. Page 172 of 982 REJ09B0465-0300 Rev. 3.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) State Transition Figure 7.4 shows the state transitions in boot mode. (Adjusts bit rates.) Receives H'00, ..., H'00. Transmits H'00. (Signals adjustment completion.) Boot mode is initiated. (reset in boot mode) Adjusts bit rates. 1. Receives H'55. 2. Receives an inquiry/ selection command. Waits for an inquiry/ selection command. Executes processing in response to the inquiry/ selection command.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 1. After boot mode is initiated, this LSI adjusts the SCI3_1 bit rate so that it should match the host's bit rate. 2. This LSI sends the requested information to the host in response to inquiries regarding the size, configuration, and start addresses of the user ROM areas, information on the supported devices, etc. 3.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Block 2 Block 3 Programming end area Block 4 Before reprogramming erase blocks 3 and 4 on which the programming end command is issued, erase the blocks 3 and 4. Block 5 Figure 7.5 Example of Erase Block Including Programmed Area 7.5.2 Specifications of Standard Serial Communication Interface in Boot Mode The boot program activated in boot mode communicates with the host via the on-chip SCI3_1.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 7.6 shows the boot program states and processing flow. Reset Bit-rate adjustment state Inquiry/selection state Inquiry Selection Processes inquiry. Enters the programming/ erasure state. Processes selection. Processes userROM-area erasure. Programming/ erasure state Programming Processes programming. Erasure Processes erasure. Lock bits Checking Processes lock bits. Processes checking. Figure 7.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (1) Bit-Rate Adjustment State In the bit-rate adjustment state, the boot program measures the low-level period of H'00 transmitted from the host and calculates the bit rate according to the measurement. The bit rate can be changed using the new-bit-rate selection command. On completion of bit rate adjustment, the boot program enters the inquiry/selection state. Figure 7.7 shows the sequence of bit rate adjustment.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 5. Response to a memory read command This response includes 4-byte size information.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 7 ROM • Data size (4 bytes): Size (four-byte length) of data in the response to the memory read command. (3) Inquiry/Selection State In this state, the boot program returns the information on the flash ROM in response to inquiry commands from the host, and selects the device, clock mode, and bit rate in response to the relevant selection commands. Table 7.5 lists inquiry/selection commands. REJ09B0465-0300 Rev. 3.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 7.5 Inquiry/Selection Commands Command Command Name Function H'20 Supported-device inquiry Obtains the device code and product name. H'10 Device selection Selects a device (code) H'21 Clock mode inquiry Obtains the number of selectable clock modes and the values corresponding to each of the modes.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group All the commands in table 7.5 except for the boot-program-state inquiry command (H'4F) are valid until the boot program accepts the programming/erasure state transition command (H'40). That is, until the transition command is accepted, the host can repeatedly send inquiry and selection commands in table 7.5.
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Section 7 ROM (b) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Device Selection In response to a device selection command, the boot program sets the specified supported device as the selected device. The boot program will return the information on the selected device in response to the subsequent inquiries. Command H'10 Size Device code SUM • Command H'10 (1 byte): Device selection • Size (1 byte): The number of characters in the device-code field (fixed to four).
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • • • • (d) Response H'31 (1 byte): Response to a clock mode inquiry command Size (1 byte): The total size of the mode fields Mode (1 byte): Selectable clock modes (example: H'00 denotes clock mode) SUM (1 byte): Checksum Clock Mode Selection In response to a clock mode selection command, the boot program sets the specified clock mode as the selected clock mode.
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Section 7 ROM (e) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Frequency-Division-Ratio Inquiry In response to a frequency-division-ratio inquiry command, the boot program returns the information on the selectable frequency division ratios.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (f) Section 7 ROM Operating-Frequency Inquiry In response to an operating-frequency inquiry command, the boot program returns the number of operating frequency types and the respective maximum and minimum frequencies.
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Section 7 ROM (g) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Programmable ROM Information Inquiry In response to a programmable ROM information inquiry command, the boot program returns the number of programmable ROM areas and their addresses.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • Response H'36 (1 byte): Response to an erasure-block information inquiry command • Size (2 bytes): The total size of the number-of-blocks, start-address-of-the-block, and endaddress-of-the-block fields.
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Section 7 ROM (j) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Data Flash Inquiry In response to a data flash inquiry command, the boot program returns an indicator of whether or not data-flash memory is present.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 7 ROM • Number of areas (1 byte): The number of contiguous data-flash areas H'01: Consecutive data flash areas H'00: No data flash area • Start address of an area (4 bytes): Address where the area starts. This value is omitted if there is no data-flash area. • End address of an area (4 bytes): Address where the area ends. This value is omitted if there is no data-flash area.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (m) New Bit-Rate Selection In response to a new bit-rate selection command, the boot program changes the bit rate settings to those of the specified one, and responds to the acknowledgement from the host at the new bit rate. The new bit-rate selection command should be transmitted after the clock-mode selection command.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 7 ROM • Frequency division ratio 2 (1 byte): Frequency division ratio for the peripheral operating frequency. The negative numerical value by which the frequency is divided. (Example: H'FE (-2) when the frequency is divided by two.) • SUM (1 byte): Checksum Response H'06 • Response H'06 (1 byte): Response to the new bit-rate selection command The ACK code is returned when selection is possible.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 3. Operating frequency The operating frequency is calculated from the received input frequency and frequency division ratio. The input frequency is the frequency of the clock signal supplied to the LSI, whereas the operating frequency is the frequency at which the LSI actually operates. The following formula is used for the calculation.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Boot program Host Selects the new-bit-rate selection command. H'06 (ACK) Waits for one-bit period at the selected bit rate. Sets the new bit rate. Sets the new bit rate. H'06 (ACK) at the new bit rate H'06 (ACK) at the new bit rate Figure 7.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • Error response H'C0 (1 byte): Error response to the programming/erasure state transition command. • Error code H'51 (1 byte): Erasure error indicating that erasure was unsuccessful because of an error. (6) Programming/Erasure State Transition (With ID Checking) In response to a programming/erasure state transition command, the boot program checks the ID code if the location of user ROM indicated in table 7.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 7 ROM • ID (16 bytes): The ID value is in the eight lower-order bytes. The value of the eight higherorder bytes is H'FF. For example, when the ID is the eight-byte value H'55112233, H'44556677, the value H'FFFFFFFF, H'FFFFFFFF, H'55112233, H'44556677 will match the ID. When the ID is the six-byte value H'55112233, H'4455, the value H'FFFFFFFF, H'FFFFFFFF, H'55112233, H'4455FFFF will match the ID.
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Section 7 ROM (9) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Command Errors Command errors are caused by undefined commands, incorrect command sequence, and unacceptable commands. For example, sending a clock-mode selection command before a device selection command and sending an inquiry command after a programming/erasure state transition command both cause command errors.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (11) Programming/Erasure State In the programming/erasure state, the boot program selects the form of programming in response to the programming selection command and then writes the data in response to the 128-byte programming command; or the boot program erases the desired blocks in response to the erasure selection and block erasure commands. Table 7.7 lists the programming/erasure commands. Table 7.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Next, the host sends the 128-byte programming command. The boot program assumes that the 128 bytes of data included in the 128-byte programming command should be programmed according to the form of programming selected by the preceding programming selection command. To program more than 128 bytes, repeatedly send 128-byte programming commands.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Host Boot program Erasure selection (H'48) Transfers the erasurecontrol program. ACK Block erasure (block number) Repeats the steps. Performs erasure. ACK Block erasure (block number = H'FF) ACK Figure 7.
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Section 7 ROM (b) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 128-Byte Programming In response to a 128-byte programming command, the boot program programs the user ROM area according to the programming-control program transferred in response to the user-ROM-area programming selection command.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group The specified address should be on a boundary corresponding to the unit of programming (programming size). For example, when the programming size is 128 bytes, the lower 8 bits of the address should be either H'00 or H'80. When less than 128 bytes of data are to be programmed, the host should transmit the data after padding the vacant bytes with H'FF.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • Response H'06 (1 byte): Response to an erasure selection command. The ACK code is returned upon completion of transferring the erasure-control program.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group On receiving the command with H'FF as the block number, the boot program terminates erasure processing and waits for the next programming/erasure selection command.
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Section 7 ROM Response H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group H'52 Reading size Data … SUM • • • • Response H'52 (1 byte): Response to a memory read command Reading size (4 bytes): The amount of data to be read Data (128 bytes): The specified amount of data to be read out starting at the specified address SUM (1 byte): Checksum Error response H'D2 ERROR • Error response H'D2 (1 byte): Error response to a memory read command • ERROR (1 byte): Error code H'11: Check
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (g) Programmable ROM Blank Check In response to a programmable ROM blank check command, the boot program checks to see if the whole the programmable ROM area is blank and returns the result.
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Section 7 ROM (i) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Data Flash Blank Check In response to a data flash blank check command, the boot program checks to see if the whole data flash areas are blank and returns an indicator of the result. Command H'62 • Command H'62 (1 byte): Data flash blank check Response H'06 • Response H'06 (1 byte): Response to a data flash blank check command. The ACK code is returned when the whole areas are blank (all bytes are H'FF).
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • STATUS (1 byte): The value 0 for bit 6 indicates the locked state. • STATUS (1 byte): The value 1 for bit 6 indicates the unlocked state. Error response H'F1 ERROR • Error response H'F1 (1 byte): Error response to a lock-bit state read command • ERROR (1 byte): Error code H'11: Checksum error H'2A: Address error. This error indicates that the specified block address is incorrect.
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Section 7 ROM (l) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Enabling Lock Bit This command enables the function of lock bits. Command H'7A • Command H'7A (1 byte): Enabling lock bit Response H'06 • Response H'06 (1 byte): Response to an enabling-lock-bit command (ACK code) (m) Disabling Lock Bit This command disables the function of lock bits.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 7 ROM • ERROR (1 byte): Error information ERROR = 0: Success ERROR ≠ 0: Error • SUM (1 byte): Checksum Table 7.
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Section 7 ROM Table 7.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Reset-start No Programming/erasing Yes Transfer the programming/erasurecontrol program to RAM. Branch to the application program in flash memory. Branch to the programming/erasurecontrol program in RAM. Execute the programming/erasurecontrol program (reprogram the flash memory). Branch to the application program in flash memory. Figure 7.
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Section 7 ROM 7.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Programming/Erasing The CPU reprogramming method is employed to program and erase flash memory on board, in which the CPU executes software commands. 7.6.1 Software Commands Table 7.10 shows a list of software commands through word instructions and table 7.11 shows a list of software commands through byte instructions.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 7.11 Software Commands (in Byte Instructions: FMWUS = 0) First Command Cycle Third Command Second to Fifth Command Use in Command Cycle Command Cycle Modes Software Command Mode Addr.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Flow of initialization for EW0 mode*1 1 Start Transfer the overwriting program to RAM. Command issued for the program region? No Yes Set the interrupt vector offset by VOFR and place the interrupt vectors in RAM.*1 FMLBD = 1 Command issued for data flash? Jump to the overwriting program in RAM.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) Section 7 ROM Erasure When H'20 is written in the first command cycle and H'D0 is written to any address in the block in the second command cycle, erase/erase-verify of the specified block is automatically started. Completion of erasure is indicated by the FMRDY bit in FLMSTR. The FMRDY bit is read as 0 during erasure, and read as 1 after erasure completion.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start Write software command H'20. Write H'D0 to any address in the specified block. FMRDY = 1? No Yes Full status check Erasure end Figure 7.14 Flowchart When Erase-Suspend Function is Not Used Page 216 of 982 REJ09B0465-0300 Rev. 3.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (EW0 mode) Interrupt request*1*2 Start FMSPEN = 1 FMSPREQ = 1 Write software command H'20. FMRDY = 1? No Yes Write H'D0 to any address in the specified block. Access to flash memory FMSPREQ = 0 FMRDY = 1? No RTE Yes Full status check Erasure end (EW1 mode) Interrupt request*2 Start Access to flash memory FMSPEN = 1 RTE Write software command H'20. Write H'D0 to any address in the specified block.
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Section 7 ROM (3) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Programming A programming command is used to program data in the flash memory in 4-byte units. Command or data size can be set depending on the FMWUS bit in FLMCR1. Setting the FMWUS bit to 0 enables using byte instructions. When H'41 is written in the first command cycle and data is written to the programming address in the second through fifth command cycles, programming and verifying are automatically started*.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start Write software command H'41 to the programming address. Write data to the programming address. FMRDY = 1? No Yes Full status check Programming end Figure 7.16 Programming Flowchart REJ09B0465-0300 Rev. 3.
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Section 7 ROM (4) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Blank Checking When H'25 is written in the first command cycle and H'D0 is written to any address in the block in the second command cycle, blank checking of the specified block is started. Completion of blank checking is indicated by the FMRDY bit in FLMSTR. The FMRDY bit is read as 0 during blank checking, and read as 1 after blank checking completion.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (5) Lock-Bit Program When H'77 is written in the first command cycle and H'D0 is written to any address in the block in the second command cycle, lock-bit programming of the specified block is started. Completion of lock-bit programming is indicated by the FMRDY bit in FLMSTR. The FMRDY bit is read as 0 during lock-bit programming, and read as 1 after lock-bit programming completion.
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Section 7 ROM (6) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Read-Array Command A read-array command is to cause a transition to a mode in which data can be read from flash memory. When H'FF is written in the first command cycle, a transition to read array mode is caused. When the specified addresses are read out in the subsequent command cycles, data is read from the specified addresses.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 7.12 Bit Values in FLMSTR and Corresponding Errors Bit Values in FLMSTR FMEBSF FMPRSF Error Error Generation Conditions 0 0 Successful end 0 1 Programming error The programming command is executed and results in unsuccessful programming. Lock-bit programming error The lock-bit program command is executed and results in unsuccessful programming.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Full status check FMEBSF = 1 and FMPRSF = 1 Yes Command sequence error No Erasure/blank-checking status flag FMEBSF = 1 Yes Erasure error or blank checking error Yes Programming error or lock-bit programming error No Programming status flag FMPRSF = 1 Full status check end Command sequence error Erasure error Execute the clear-status command. (Clear the status flag to 0). Execute the clear-status command.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (10) Example of Issuing Commands Figures 7.20 and 7.21 show examples of issuing programming commands and erasure commands, respectively. Figure 7.22 shows examples of issuing read-array commands. Using word-length instructions to issue programming commands (FMWUS = 1) Target address for writing Data H'004000 H'12 H'004001 H'34 H'004002 H'56 H'004003 H'78 [Programming Example] @MOV.W #H'4141,R0 @MOV.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Using word-length instructions to issue erasure commands (FMWUS = 1) [Erasure Setting] Erasure block = Data flash A [Programming Example] @MOV.W @MOV.W @MOV.W @MOV.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Using word-length instructions to issue read-array commands (FMWUS = 1) [Read-Array Setting] Address = Program-ROM area [Programming Example] ; Read-array command @MOV.W #H'FFFF, R0 @MOV.W R0, @H'00000000 ; First command Issuing of first command Address bus Data bus Reading can proceed.
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Section 7 ROM 7.7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Protection Three modes are available to protect the flash memory against reading, programming, and erasing: software protection, lock-bit protection, and protection to restrict access in programmer mode and boot mode. 7.7.1 Software Protection Software commands can be disabled by clearing the FMCMDEN bit in the flash memory control register (FLMCR1) through software.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 7.7.3 PROM Programmer Protection/Boot Mode Protection PROM programmer protection/boot mode protection is enabled by writing the specified data to the user ROM area shown in the table 7.13. The protection function can be disabled by using a PROM programmer or on-board programmer to delete the entire user ROM area. Table 7.14 shows the specifications for PROM programmer protection and table 7.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 7.15 Specifications for Boot Mode Protection Control code* Protection State Operation in Serial Connection Other than above Protection is disabled. Entire blocks are deleted. H'45 ID authentication protection 1*2 Possible for reading/programming/erasing if the ID was authenticated. If the ID was not authenticated, entire blocks are deleted.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 7.9 Usage Notes (1) Prohibited Instruction In EW0 mode, the following instruction cannot be used because it refers to the data in the flash memory area. • TRAPA (2) Interrupts Table 7.16 shows interrupt handling in CPU reprogramming mode. Table 7.
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Section 7 ROM Mode State EW1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group When Watchdog Timer Reset, LVD Reset, Software Reset, or When Interrupt Request is Pin Reset, Interrupt Request is Received Generated During erasure command Erasure is given priority, (erase-suspend function keeping the interrupt not used) request waiting. When erasure is completed, execution of the interrupt processing is started.
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Section 7 ROM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group The example below is of code for use when the FMCMDEN and FMLBD bits in FLMCR1 are to be changed from 0 to 1. MOV.B @FLMCR1,R0L :FLMCR1=H'04 R0L=H'04 R0H=H'xx MOV.B @FLMCR1,R0H :FLMCR1=H'04 R0L=H'04 R0H=H'04 BSET #0,R0H :FLMCR1=H'04 R0L=H'04 R0H=H'05 BSET #3,R0H :FLMCR1=H'04 R0L=H'04 R0H=H'0D MOV.B R0L,@FLMCR1 :FLMCR1=H'04 R0L=H'04 R0H=H'0D MOV.
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Section 7 ROM (9) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Frequent Reprogramming For systems that will be frequently reprogrammed, follow the below procedure to reduce the effective number of reprogramming operations. As far as is possible, write data at appropriately increasing addresses until no blank areas remain, and then erase the whole block.
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Section 8 RAM H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 8 RAM The H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, and H8S/20235 Group LSIs have an on-chip high-speed static RAM. The RAM is connected to the CPU via a 16-bit data bus, enabling the CPU to access both byte data and word data in one state.
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Section 8 RAM Page 236 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300 Rev. 3.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 9 Peripheral I/O Mapping Controller The peripheral function mapping controller (PMC) is composed of registers that are used to select the functions of multiplexed pins. The multiplexed pins are divided into two groups: group 1 and group 2. Group 1 consists of ports 1 to 3, 5, and 6, and group 2 consists of ports 8, 9*, and A. Tables 9.1 and 9.
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Section 9 Peripheral I/O Mapping Controller Table 9.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 9.
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Section 9 Peripheral I/O Mapping Controller 9.1.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Peripheral Function Mapping Register Write-Protect Register (PMCWPR) Address: H'FF0065 Bit: b7 b6 b5 b4 b3 b2 b1 b0 B0WI PMCRWE ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 B0WI Bit 6 write protect 0: Writing to PMCRWE (bit 6 in this register) is enabled. W 1: Writing to the PMCRWE bit is disabled.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 9.1.
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Section 9 Peripheral I/O Mapping Controller (b) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port 1 Peripheral Function Mapping Register 2 (PMCR12) Address: H'FF0041 Bit: b7 b6 0 b4 P13MD[2:0] ⎯ Value after reset: b5 0 0 b3 b2 b1 P12MD[2:0] ⎯ 1 0 b0 0 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (c) Port 1 Peripheral Function Mapping Register 3 (PMCR13) Address: H'FF0042 Bit: b6 b7 b4 P15MD[2:0] ⎯ Value after reset: b5 0 0 0 b3 b2 b0 P14MD[2:0] ⎯ 1 b1 0 0 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller (d) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port 1 Peripheral Function Mapping Register 4 (PMCR14) Address: H'FF0043 Bit: b7 b6 0 b4 P17MD[2:0] ⎯ Value after reset: b5 0 0 b3 b2 b1 P16MD[2:0] ⎯ 1 0 b0 0 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) Port 2 (a) Port 2 Peripheral Function Mapping Register 1 (PMCR21) Address: H'FF0044 Bit: b6 b7 Value after reset: b5 b4 P21MD[2:0] ⎯ 0 0 1 b3 b2 0 0 b1 b0 P20MD[2:0] ⎯ 0 1 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller (b) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port 2 Peripheral Function Mapping Register 2 (PMCR22) Address: H'FF0045 Bit: b7 b6 0 b4 P23MD[2:0] ⎯ Value after reset: b5 0 1 b3 b2 0 b0 P22MD[2:0] ⎯ 0 b1 0 1 0 Bit Bit Name Initial Value Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (c) Port 2 Peripheral Function Mapping Register 3 (PMCR23) Address: H'FF0046 Bit: b6 b7 b4 P25MD[2:0] ⎯ Value after reset: b5 0 0 1 b3 b2 b1 P24MD[2:0] ⎯ 0 b0 0 0 1 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller (d) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port 2 Peripheral Function Mapping Register 4 (PMCR24) Address: H'FF0047 Bit: b7 b6 0 b4 P27MD[2:0] ⎯ Value after reset: b5 0 1 b3 b2 0 b0 P26MD[2:0] ⎯ 0 b1 0 1 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (3) Port 3 (a) Port 3 Peripheral Function Mapping Register 1 (PMCR31) Address: H'FF0048 Bit: b6 b7 Value after reset: b5 b4 P31MD[2:0] ⎯ 0 0 1 b3 b2 1 0 b1 b0 P30MD[2:0] ⎯ 0 1 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller (b) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port 3 Peripheral Function Mapping Register 2 (PMCR32) Address: H'FF0049 Bit: b7 b6 0 b4 P33MD[2:0] ⎯ Value after reset: b5 0 1 b3 b2 0 b0 P32MD[2:0] ⎯ 1 b1 0 1 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (c) Port 3 Peripheral Function Mapping Register 3 (PMCR33) Address: H'FF004A Bit: b6 b7 b4 P35MD[2:0] ⎯ Value after reset: b5 0 0 1 b3 b2 b1 P34MD[2:0] ⎯ 1 0 b0 0 1 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller (d) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port 3 Peripheral Function Mapping Register 4 (PMCR34) Address: H'FF004B Bit: b7 b6 0 b4 P37MD[2:0] ⎯ Value after reset: b5 0 1 b3 b2 b0 P36MD[2:0] ⎯ 1 b1 0 0 1 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (4) Port 5 (a) Port 5 Peripheral Function Mapping Register 1 (PMCR51) Address: H'FF0050 Bit: b6 b7 Value after reset: b5 b4 P51MD[2:0] ⎯ 0 1 0 b3 b2 0 0 b1 b0 P50MD[2:0] ⎯ 1 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller (b) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port 5 Peripheral Function Mapping Register 2 (PMCR52) Address: H'FF0051 Bit: b7 b6 0 b4 P53MD[2:0] ⎯ Value after reset: b5 1 0 b3 b2 b1 P52MD[2:0] ⎯ 0 0 b0 1 0 0 Bit Symbol Bit Name Description 7 ⎯ Reserved This bit is always read as 0. The write value should ⎯ always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (c) Port 5 Peripheral Function Mapping Register 3 (PMCR53) Address: H'FF0052 Bit: b7 b6 0 b4 P55MD[2:0] ⎯ Value after reset: b5 1 0 b3 b2 b0 P54MD[2:0] ⎯ 0 b1 0 1 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should ⎯ always be 0.
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Section 9 Peripheral I/O Mapping Controller (d) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port 5 Peripheral Function Mapping Register 4 (PMCR54) Address: H'FF0053 Bit: b7 b6 0 b4 P57MD[2:0] ⎯ Value after reset: b5 1 0 b3 b2 0 b0 P56MD[2:0] ⎯ 0 b1 1 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 9 Peripheral I/O Mapping Controller Notes: 1. When the IIC2/SSU is used as the IIC2 function, the SCL and SDA functions can be allocated to the P56 and P57 pins only because SCL and SDA require buffers dedicated for IIC input/output. The PMC can not be used to allocate the SCL and SDA 2 functions to other pins. When the IIC2/SSU is used for the SSU function except * , there is no restriction.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (5) Port 6 (a) Port 6 Peripheral Function Mapping Register 1 (PMCR61) Address: H'FF0054 Bit: b7 b6 Value after reset: 0 b5 b4 P61MD[2:0] ⎯ 1 0 b3 b2 b1 1 0 b0 P60MD[2:0] ⎯ 1 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (b) Port 6 Peripheral Function Mapping Register 2 (PMCR62) Address: H'FF0055 Bit: b7 b6 0 b4 P63MD[2:0] ⎯ Value after reset: b5 1 0 b3 b2 0 b0 P62MD[2:0] ⎯ 1 b1 1 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller (c) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port 6 Peripheral Function Mapping Register 3 (PMCR63) Address: H'FF0056 Bit: b7 b6 0 b4 P65MD[2:0] ⎯ Value after reset: b5 1 0 b3 b2 b1 P64MD[2:0] ⎯ 1 b0 0 1 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should ⎯ always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (d) Port 6 Peripheral Function Mapping Register 4 (PMCR64) Address: H'FF0057 Bit: b7 b6 0 b4 P67MD[2:0] ⎯ Value after reset: b5 1 0 b3 b2 b0 P66MD[2:0] ⎯ 1 b1 0 1 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller 9.1.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port Group 2 Peripheral Function Mapping Registers 1 to 4 (PMCRn1 to PMCRn4 (n = 8, 9, and A) (1) Port 8 (a) Port 8 Peripheral Function Mapping Register 3 (PMCR83) Address: H'FF005E Bit: b7 b6 0 b4 P85MD[2:0] ⎯ Value after reset: b5 1 0 0 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ 0 0 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (b) Port 8 Peripheral Function Mapping Register 4 (PMCR84) Address: H'FF005F Bit: b6 b7 b4 P87MD[2:0] ⎯ Value after reset: b5 0 1 0 b3 b2 0 b0 P86MD[2:0] ⎯ 0 b1 1 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) Port 9 (a) Port 9 Peripheral Function Mapping Register 1 (PMCR91) Address: H'FF0060 Bit: b7 b6 Value after reset: 0 b5 b4 P91MD[2:0] ⎯ 1 0 b3 b2 1 0 b1 b0 P90MD[2:0] ⎯ 1 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (b) Port 9 Peripheral Function Mapping Register 2 (PMCR92) Address: H'FF0061 Bit: b6 b7 b4 P93MD[2:0] ⎯ Value after reset: b5 0 1 0 b3 b2 0 b0 P92MD[2:0] ⎯ 1 b1 1 0 1 Bit Symbol Bit Name Description 7 ⎯ Reserved This bit is always read as 0. The write value should ⎯ always be 0.
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Section 9 Peripheral I/O Mapping Controller (c) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port 9 Peripheral Function Mapping Register 3 (PMCR93) Address: H'FF0062 Bit: b7 b6 0 b4 P95MD[2:0] ⎯ Value after reset: b5 1 0 b3 b2 b1 P94MD[2:0] ⎯ 1 0 b0 1 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (d) Port 9 Peripheral Function Mapping Register 4 (PMCR94) Address: H'FF0063 Bit: b6 b7 b4 P97MD[2:0] ⎯ Value after reset: b5 0 1 0 b3 b2 0 b0 P96MD[2:0] ⎯ 1 b1 1 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (3) Port A (a) Port A Peripheral Function Mapping Register 3 (PMCRA3) Address: H'FF0066 Bit: b7 b6 Value after reset: 0 b5 b4 PA5MD[2:0] ⎯ 0 0 b3 b2 b1 0 0 b0 PA4MD[2:0] ⎯ 0 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (b) Port A Peripheral Function Mapping Register 4 (PMCRA4) Address: H'FF0067 Bit: b7 b6 0 b4 PA7MD[2:0] ⎯ Value after reset: b5 0 0 b3 b2 0 b0 PA6MD[2:0] ⎯ 0 b1 0 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is always read as 0. The write value should always be 0.
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Section 9 Peripheral I/O Mapping Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 9.2 Usage Notes 9.2.1 Procedures for Setting Multiplexed Port Functions Use the following procedures to set a function for a multiplexed port. 1. 2. 3. 4. 5. Clear the relevant port mode register (PMR) bit to 0 to select the general input function. Set PMCWPR to enable writing to the relevant peripheral function mapping register (PMCR).
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Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 10 I/O Ports The H8S/20103 and H8S/20115 Groups have fifty-five general I/O ports, and the H8S/20223, H8S/20203, H8S/20215, and H8S/20235 Groups each have sixty-nine general I/O ports.
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Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port 1 has the following registers. • • • • • Port mode register 1 (PMR1) Port control register 1 (PCR1) Port data register 1 (PDR1) Port pull-up control register 1 (PUCR1) Port drive control register 1 (PDVR1) 10.1.
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Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.1.2 Port Control Register 1 (PCR1) Address: H'FFFFF0 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PCR17 PCR16 PCR15 PCR14 PCR13 PCR12 PCR11 PCR10 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PCR17 Port 17 control R/W 6 PCR16 Port 16 control 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port.
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Section 10 I/O Ports 10.1.
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Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.1.4 Port Pull-Up Control Register 1 (PUCR1) Address: H'FF0010 Bit: b7 b6 b5 b4 b3 b2 b1 b0 PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 PUCR17 Port 17 pull-up control 0: The pull-up MOS of corresponding pin is disabled.
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Section 10 I/O Ports 10.1.
PAGE 303
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.2 Port 2 Figure 10.2 shows the pin configuration of port 2.
PAGE 304
Section 10 I/O Ports 10.2.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port Mode Register 2 (PMR2) Address: H'FF0001 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PMR27 PMR26 PMR25 PMR24 PMR23 PMR22 PMR21 PMR20 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PMR27 Port 27 mode 0: General I/O port R/W 6 PMR26 Port 26 mode R/W 5 PMR25 Port 25 mode 1: The function selected by the peripheral function mapping controller (PMC).
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Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.2.2 Port Control Register 2 (PCR2) Address: H'FFFFF1 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PCR27 PCR26 PCR25 PCR24 PCR23 PCR22 PCR21 PCR20 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PCR27 Port 27 control R/W 6 PCR26 Port 26 control 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port.
PAGE 306
Section 10 I/O Ports 10.2.
PAGE 307
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.2.4 Port Pull-Up Control Register 2 (PUCR2) Address: H'FF0011 Bit: b7 b6 b5 b4 b3 b2 b1 b0 PUCR27 PUCR26 PUCR25 PUCR24 PUCR23 PUCR22 PUCR21 PUCR20 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 PUCR27 Port 27 pull-up control 0: The pull-up MOS of corresponding pin is disabled.
PAGE 308
Section 10 I/O Ports 10.2.
PAGE 309
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.3 Port 3 Figure 10.3 shows the pin configuration of port 3. P37/TXD_3 P36/RXD_3 P35/SCK3_3 P34 P33 P32 P31 P30 H8S/20103 Group H8S/20115 Group Port 3 Port 3 H8S/20203 Group H8S/20223 Group H8S/20215 Group H8S/20235 Group P37/TXD_3 P36/RXD_3 P35/SCK3_3 P34/FTCI P33/FTIOD P32/FTIOC P31/FTIOB P30/FTIOA Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.
PAGE 310
Section 10 I/O Ports 10.3.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port Mode Register 3 (PMR3) Address: H'FF0002 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PMR37 PMR36 PMR35 PMR34 PMR33 PMR32 PMR31 PMR30 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PMR37 Port 37 mode 0: General I/O port R/W 6 PMR36 Port 36 mode R/W 5 PMR35 Port 35 mode 1: The function selected by the peripheral function mapping controller (PMC).
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Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.3.2 Port Control Register 3 (PCR3) Address: H'FFFFF2 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PCR37 PCR36 PCR35 PCR34 PCR33 PCR32 PCR31 PCR30 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PCR37 Port 37 control R/W 6 PCR36 Port 36 control 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port.
PAGE 312
Section 10 I/O Ports 10.3.
PAGE 313
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.3.4 Port Pull-Up Control Register 3 (PUCR3) Address: H'FF0012 Bit: b7 b6 b5 b4 b3 b2 b1 b0 PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 PUCR37 Port 37 pull-up control 0: The pull-up MOS of corresponding pin is disabled.
PAGE 314
Section 10 I/O Ports 10.3.
PAGE 315
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.4 Port 5 Port 5 Figure 10.4 shows the pin configuration of port 5. P57/SCL/SSI P56/SDA/SCS P55/SSCK P54/SSO P53/TGIOB P52/TGIOA P51/TCLKB P50/TCLKA Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.4 Port 5 Pin Configuration Port 5 has the following registers.
PAGE 316
Section 10 I/O Ports 10.4.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port Mode Register 5 (PMR5) Address: H'FF0004 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PMR57 PMR56 PMR55 PMR54 PMR53 PMR52 PMR51 PMR50 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PMR57 Port 57 mode 0: General I/O port R/W 6 PMR56 Port 56 mode R/W 5 PMR55 Port 55 mode 1: The function selected by the peripheral function mapping controller (PMC).
PAGE 317
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.4.2 Port Control Register 5 (PCR5) Address: H'FFFFF4 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PCR57 Port 57 control R/W 6 PCR56 Port 56 control 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port.
PAGE 318
Section 10 I/O Ports 10.4.
PAGE 319
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.4.4 Port Pull-Up Control Register 5 (PUCR5) Address: H'FF0014 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 — — PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved 6 ⎯ Reserved These bits are read as 0. The write value should be ⎯ 0.
PAGE 320
Section 10 I/O Ports 10.4.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port Drive Control Register 5 (PDVR5) Address: H'FF0034 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ PDVR55 PDVR54 PDVR53 PDVR52 PDVR51 PDVR50 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is read as 0. The write value should be 0.
PAGE 321
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.5 Port 6 Port 6 Figure 10.5 shows the pin configuration of port 6. P67/FTIOD1 P66/FTIOC1 P65/FTIOB1 P64/FTIOA1 P63/FTIOD0 P62/FTIOC0 P61/FTIOB0 P60/FTIOA0 Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.5 Port 6 Pin Configuration Port 6 has the following registers.
PAGE 322
Section 10 I/O Ports 10.5.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port Mode Register 6 (PMR6) Address: H'FF0005 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PMR67 PMR66 PMR65 PMR64 PMR63 PMR62 PMR61 PMR60 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PMR67 Port 67 mode 0: General I/O port R/W 6 PMR66 Port 66 mode R/W 5 PMR65 Port 65 mode 1: The function selected by the peripheral function mapping controller (PMC).
PAGE 323
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.5.2 Port Control Register 6 (PCR6) Address: H'FFFFF5 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PCR67 PCR66 PCR65 PCR64 PCR63 PCR62 PCR61 PCR60 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PCR67 Port 67 control R/W 6 PCR66 Port 66 control 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port.
PAGE 324
Section 10 I/O Ports 10.5.
PAGE 325
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.5.4 Port Pull-Up Control Register 6 (PUCR6) Address: H'FF0015 Bit: b7 b6 b5 b4 b3 b2 b1 b0 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 PUCR67 Port 67 pull-up control 0: The pull-up MOS of corresponding pin is disabled.
PAGE 326
Section 10 I/O Ports 10.5.
PAGE 327
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.6 Port 8 Port 8 Figure 10.6 shows the pin configuration of port 8. P87/TREO P86/TRBO P85/TRAIO Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.6 Port 8 Pin Configuration Port 8 has the following registers.
PAGE 328
Section 10 I/O Ports 10.6.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port Mode Register 8 (PMR8) Address: H'FF0005 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PMR67 PMR66 PMR65 PMR64 PMR63 PMR62 PMR61 PMR60 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PMR87 Port 87 mode 0: General I/O port R/W 6 PMR86 Port 86 mode R/W 5 PMR85 Port 85 mode 1: The function selected by the peripheral function mapping controller (PMC).
PAGE 329
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.6.2 Port Control Register 8 (PCR8) Address: H'FFFFF7 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PCR87 PCR86 PCR85 ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PCR87 Port 87 control 6 PCR86 Port 86 control 5 PCR85 Port 85 control 0: When the corresponding pin is designated as a R/W general I/O port, the pin functions as an input R/W port.
PAGE 330
Section 10 I/O Ports 10.6.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port Data Register 8 (PDR8) Address: H'FFFFE7 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PDR87 PDR86 PDR85 ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PDR87 Port 87 data 0: Low level R/W 6 PDR86 Port 86 data 1: High level R/W 5 PDR85 Port 85 data PDR8 is a register that stores output data for port R/W 8 pins.
PAGE 331
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.6.4 Port Pull-Up Control Register 8 (PUCR8) Address: H'FF0017 Bit: b7 b6 b5 b4 b3 b2 b1 b0 PUCR87 PUCR86 PUCR85 ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 PUCR87 Port 87 pull-up control 0: The pull-up MOS of corresponding pin is disabled. R/W 6 PUCR86 Port 86 pull-up control 1: The pull-up MOS of corresponding pin is enabled.
PAGE 332
Section 10 I/O Ports 10.6.
PAGE 333
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.7 Port 9 Port 9 Figure 10.7 shows the pin configuration of port 9. Port 9 is not available on the H8S/20103 and H8S/20115 Groups. P97/FTIOD3 P96/FTIOC3 P95/FTIOB3 P94/FTIOA3 P93/FTIOD2 P92/FTIOC2 P91/FTIOB2 P90/FTIOA2 Note: Only the functions initially selected by PMCR are shown following the port pin names. Figure 10.7 Port 9 Pin Configuration Port 9 has the following registers.
PAGE 334
Section 10 I/O Ports 10.7.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port Mode Register 9 (PMR9) Address: H'FF0008 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PMR97 PMR96 PMR95 PMR94 PMR93 PMR92 PMR91 PMR90 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PMR97 Port 97 mode 0: General I/O port R/W 6 PMR96 Port 96 mode R/W 5 PMR95 Port 95 mode 1: The function selected by the peripheral function mapping controller (PMC).
PAGE 335
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.7.2 Port Control Register 9 (PCR9) Address: H'FFFFF8 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PCR97 PCR96 PCR95 PCR94 PCR93 PCR92 PCR91 PCR90 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PCR97 Port 97 control R/W 6 PCR96 Port 96 control 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input port.
PAGE 336
Section 10 I/O Ports 10.7.
PAGE 337
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.7.4 Port Pull-Up Control Register 9 (PUCR9) Address: H'FF0018 Bit: b7 b6 b5 b4 b3 b2 b1 b0 PUCR97 PUCR96 PUCR95 PUCR94 PUCR93 PUCR92 PUCR91 PUCR90 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 PUCR97 Port 97 pull-up control 0: The pull-up MOS of corresponding pin is disabled.
PAGE 338
Section 10 I/O Ports 10.7.
PAGE 339
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.8 Port A Port A consists of general I/O pins that are also used as analog input pins for A/D converter unit 1 and unit 2 (only in the H8S/20223 and H8S/20235 Groups). The functions of PA4 to PA7 can be selected with the peripheral function mapping register of the PMC (except for the H8S/20223 and H8S/20235 Groups).
PAGE 340
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • H8S/20103 and H8S/20115 Groups 10.8.
PAGE 341
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.8.2 Port Control Register A (PCRA) Address: H'FFFFF9 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PCRA7 PCRA6 PCRA5 PCRA4 ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PCRA7 6 PCRA6 5 PCRA5 4 PCRA4 Port A7 control 0: When the corresponding pin is designated as a general I/O port, the pin functions as an input Port A6 control port.
PAGE 342
Section 10 I/O Ports 10.8.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port Data Register A (PDRA) Address: H'FFFFE9 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PDRA7 PDRA6 PDRA5 PDRA4 ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PDRA7 Port A7 data 0: Low level R/W 6 PDRA6 Port A6 data 1: High level R/W 5 PDRA5 Port A5 data 4 PDRA4 Port A4 data PDRA is a register that stores output data for port A R/W pins.
PAGE 343
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.8.4 Port Pull-Up Control Register A (PUCRA) Address: H'FF0019 Bit: b7 b6 b5 b4 b3 b2 b1 b0 PUCRA7 PUCRA6 PUCRA5 PUCRA4 ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name 7 PUCRA7* Port A7 pull-up 0: The pull-up MOS of corresponding pin is disabled. control R/W 6 PUCRA6* Port A6 pull-up 1: The pull-up MOS of corresponding pin is not enabled.
PAGE 344
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • H8S/20203 and H8S/20215 Groups 10.8.
PAGE 345
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.8.
PAGE 346
Section 10 I/O Ports 10.8.
PAGE 347
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.8.8 Port Pull-Up Control Register A (PUCRA) Address: H'FF0019 Bit: b7 b6 b5 b4 b3 b2 b1 b0 PUCRA7 PUCRA6 PUCRA5 PUCRA4 PUCRA3 PUCRA2 PUCRA1 PUCRA0 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name 7 PUCRA7* Port A7 pull-up 0: The pull-up MOS of corresponding pin is disabled. control R/W 6 PUCRA6* Port A6 pull-up 1: The pull-up MOS of corresponding pin is enabled.
PAGE 348
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • H8S/20223 and H8S/20235 Groups 10.8.9 Port Mode Register A (PMRA) Address: H'FF0009 Bit: Value after reset: Bit b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ PMRA3 PMRA2 ⎯ ⎯ 0 0 0 0 0 0 0 0 Bit Name Description R/W 7 to 4 ⎯ Reserved These bits are read as 0. The write value should be 0.
PAGE 349
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.8.
PAGE 350
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.8.
PAGE 351
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.8.12 Port Pull-Up Control Register A (PUCRA) Address: H'FF0019 Bit: b7 b6 b5 b4 b3 b2 b1 b0 PUCRA7 PUCRA6 PUCRA5 PUCRA4 PUCRA3 PUCRA2 PUCRA1 PUCRA0 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name 7 PUCRA7* Port A7 pull-up 0: The pull-up MOS of corresponding pin is disabled. control R/W 6 PUCRA6* Port A6 pull-up 1: The pull-up MOS of corresponding pin is enabled.
PAGE 352
Section 10 I/O Ports 10.9 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port B Port B Port B consists of general I/O pins that are also used as analog input pins for the A/D converter unit 1, or as analog output pins for the D/A converter. Figure 10.9 shows the pin configuration of port B. PB7/AN7/DA1 PB6/AN6/DA0 PB5/AN5 PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 10.9 Port B Pin Configuration Port B has the following registers.
PAGE 353
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.9.
PAGE 354
Section 10 I/O Ports 10.9.
PAGE 355
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.9.3 Port Pull-Up Control Register B (PUCRB) Address: H'FF001A Bit: b7 b6 b5 b4 b3 b2 b1 b0 PUCRB7 PUCRB6 PUCRB5 PUCRB4 PUCRB3 PUCRB2 PUCRB1 PUCRB0 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 PUCRB7 Port B7 pull-up 0: The pull-up MOS of corresponding pin is disabled.
PAGE 356
Section 10 I/O Ports 10.10 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port J Port J Port J consists of pins PJ1 and PJ0. These pins can also be used as external oscillation pins and clock output pin. Figure 10.10 shows the pin configuration of port J. In selection of the function of these multiplexed pins, the PMRJ register setting is given priority. PJ1/OSC2/CLKOUT PJ0/OSC1 Figure 10.10 Port J Pin Configuration Port J has the following registers.
PAGE 357
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.10.1 Port Mode Register J (PMRJ) Address: H'FF000C Bit: Value after reset: Bit Symbol 7 to 2 ⎯ 1, 0 Note: b7 b6 b5 b4 b3 b2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 b1 b0 PMRJ[1:0] 0 0 Bit Name Description R/W Reserved These bits are read as 0. The write value should be 0. ⎯ PMRJ[1:0] Port J[1:0] mode Selects PJ1 and PJ0 pin functions.
PAGE 358
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.10.2 Port Control Register J (PCRJ) Address: H'FFFFFC Bit: Value after reset: Bit Symbol b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PCRJ1 PCRJ0 0 0 0 0 0 0 0 0 Bit Name Description R/W 7 to 2 ⎯ Reserved These bits are read as 0. The write value should be 0.
PAGE 359
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.10.3 Port Data Register J (PDRJ) Address: H'FFFFEC Bit: Value after reset: Bit Symbol b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PDRJ1 PDRJ0 0 0 0 0 0 0 0 0 Bit Name Description R/W 7 to 2 ⎯ Reserved These bits are read as 0. The write value should be 0.
PAGE 360
Section 10 I/O Ports H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 10.10.4 Port Pull-Up Control Register J (PUCRJ) Address: H'FF001C Bit: Value after reset: Bit Symbol b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ PUCRJ1 PUCRJ0 0 0 0 0 0 0 0 0 Bit Name Description R/W 7 to 2 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯ 1 PUCRJ1 Port J1 pull-up control 0: The pull-up MOS of corresponding pin is disabled.
PAGE 361
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 11 Data Transfer Controller (DTC) Section 11 Data Transfer Controller (DTC) This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software to transfer data. Figure 11.1 shows a block diagram of the DTC. 11.1 Features • Transfer possible over any number of channels • Three transfer modes ⎯ Normal mode One operation transfers one byte or one word of data.
PAGE 362
Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group The DTC's register information is stored in the on-chip RAM. A 32-bit bus connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC register information.
PAGE 363
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 11.2 Section 11 Data Transfer Controller (DTC) Register Descriptions DTC has the following registers. • • • • • • DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB) The above six registers cannot be directly accessed from the CPU.
PAGE 364
Section 11 Data Transfer Controller (DTC) 11.2.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 11 Data Transfer Controller (DTC) MRA selects the DTC operating mode. • SM[1:0] bits (source address mode 1 and 0) These bits specify an SAR operation after data transfer. • DM[1:0] bits (destination address mode 1 and 0) These bits specify a DAR operation after data transfer. • MD[1:0] bits (DTC mode 1 and 0) These bits specify the DTC transfer mode.
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Section 11 Data Transfer Controller (DTC) 11.2.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group DTC Mode Register B (MRB) Address: ⎯ Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 CHNE DISEL CHNS ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Bit Symbol Bit Name Description R/W 7 CHNE DTC chain transfer enable 0: Disables chain transfer. ⎯ DTC interrupt select 0: Generates an interrupt request to the CPU only when the specified data transfer has been completed.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 11.2.
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Section 11 Data Transfer Controller (DTC) 11.2.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 11.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) Address: H'FF0534 to H'FF053B Bit: b7 b6 b5 b4 b3 b2 b1 b0 DTCEn7 DTCEn6 DTCEn5 DTCEn4 DTCEn3 DTCEn2 DTCEn1 DTCEn0 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name 7 DTCEn7 6 DTCEn6 DTC activation 0: A relevant interrupt source is not selected as a enable DTC activation source.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 11.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 11.2.8 DTC Vector Register (DTVECR) Address: H'FF053D Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description 7 SWDTE DTC software 0: Disables the DTC activation by software. activation 1: Enables the DTC activation by software.
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Section 11 Data Transfer Controller (DTC) 11.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Activation Sources The DTC operates when activated by an interrupt request or by a write to DTVECR by software. An interrupt request can be designated by the DTCER bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding bit to DTCER is cleared.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Source flag cleared Clear controller Clear DTCER On-chip peripheral module IRQ interrupt DTVECR Interrupt request Selection circuit Select Clear request DTC CPU Interrupt controller Interrupt mask Figure 11.2 Block Diagram of DTC Activation Source Control REJ09B0465-0300 Rev. 3.
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Section 11 Data Transfer Controller (DTC) 11.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Location of Register Information and DTC Vector Table Locate the register information in the on-chip RAM. Register information should be located at the address that is multiple of four. Locating the register information in address space is shown in figure 11.3. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Lower addresses 0 Start address of register information 1 2 MRA SAR MRB DAR 3 Register information CRB CRA Chain transfer MRA SAR MRB DAR CRB CRA Register information for second transfer in case of chain transfer Four bytes Figure 11.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 11.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Origin of Activation Source Timer RC* 3 Timer RD unit 0 channel 0 Timer RD unit 0 channel 1*4 Vector Vector 1 Number Address* DTCE* Priority ITCMA Input capture A/ compare match A 71 H'48E to H'48F DTCED3 High ITCMB Input capture B/ compare match B 72 H'490 to H'491 DTCED2 ITCMC Input capture C/ compare match C 73 H'492 to H'493 DTCED1 ITCMD Input capture D/ compare match D
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Section 11 Data Transfer Controller (DTC) Origin of Activation Source Activation Source Timer RD unit 1 channel 2*4 Timer RD unit 1 channel 3*4 Timer RE Timer RG Page 352 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Vector Vector 1 Number Address* DTCE* Priority ITDMA1_2 Input capture A/ compare match A 87 H'4AE to H'4AF DTCEF7 High ITDMB1_2 Input capture B/ compare match B 88 H'4B0 to H'4B1 DTCEF6 ITDMC1_2 Input capture C/ compare match C 89 H'4B2 to
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 11 Data Transfer Controller (DTC) Notes: 1. Vector address indicates the lower 11 bits of vector address when VOFR = H'0000. 2. Supported only in the H8S/20223 and H8S/20235 Groups and reserved in other products. 3. Supported only in the H8S/20103 and H8S/20115 Groups and reserved in other products. 4. Not supported in the H8S/20103 and H8S/20115 Groups, and reserved in these groups. 5.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE = 1 Yes No CHNS = 0 Yes Transfer counter = 0 or DISEL = 1 No No Yes Transfer counter = 0 Yes No DISEL = 1 Yes No Clear activation source flag Clear DTCER End Interrupt exception handling Figure 11.5 Flowchart of DTC Operation Page 354 of 982 REJ09B0465-0300 Rev. 3.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 11.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group SAR DAR Transfer Figure 11.6 Memory Mapping in Normal Mode 11.5.2 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. Table 11.6 lists the register function in repeat mode. From 1 to 256 transfers can be specified.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group SAR or DAR DAR or SAR Repeat area Transfer Figure 11.7 Memory Mapping in Repeat Mode 11.5.3 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. Table 11.7 lists the register function in block transfer mode. The block size is 1 to 256.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group First block SAR or DAR DAR or SAR Block area Transfer Nth block Figure 11.8 Memory Mapping in Block Transfer Mode 11.5.4 Chain Transfer Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB can be set independently. Figure 11.9 shows the operation of chain transfer.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Source Destination Register information CHNE=1 DTC vector address Start address of register information Register information CHNE=0 Source Destination Figure 11.9 Operation of Chain Transfer 11.5.
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Section 11 Data Transfer Controller (DTC) 11.5.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operation Timing φ DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 11.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group φ DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer information write Transfer information read Transfer information write Figure 11.12 DTC Operation Timing (Example of Chain Transfer) 11.5.7 Number of DTC Execution States Table 11.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 11.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 11.6 Procedures for Using DTC 11.6.1 Activation by Interrupt Section 11 Data Transfer Controller (DTC) The procedure for using the DTC with interrupt activation is as follows: 1. 2. 3. 4. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. Set the start address of the register information in the DTC vector address. Set the corresponding bit in DTCER to 1.
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Section 11 Data Transfer Controller (DTC) 11.7 Examples of Use of the DTC 11.7.1 Normal Mode H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group An example is shown in which the DTC is used to receive 128 bytes of data via the SCI3. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 11.7.2 Section 11 Data Transfer Controller (DTC) Chain Transfer when Transfer Counter = 0 By executing the second data transfer, and performing re-setting of the first data transfer, only when the counter value for the first data transfer is 0, 256 or more repeat transfers can be performed. An example is shown in which a 128-Kbyte input buffer is configured.
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Section 11 Data Transfer Controller (DTC) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data transfer register information Upper 8 bits of DAR Figure 11.13 Chain Transfer when Counter = 0 Page 366 of 982 REJ09B0465-0300 Rev. 3.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 11.7.3 Section 11 Data Transfer Controller (DTC) Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. 1.
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Section 11 Data Transfer Controller (DTC) 11.8 Usage Notes 11.8.1 Module Standby Mode Setting H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group DTC operation can be disabled or enabled using the module standby control register. The initial value is for DTC operation to be disabled. When the DTC is used, cancel module standby mode. Register access is disabled in module standby mode. Module standby mode cannot be set while the DTC is activated.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 12 Event Link Controller Section 12 Event Link Controller The event link controller (ELC) connects the events generated by the various peripheral modules to different modules. This function allows direct cooperation between the modules without CPU intervention. A block diagram of the ELC is shown in figure 12.1. 12.1 Overview • Fifty-seven event signals can be directly connected to modules.
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Section 12 Event Link Controller ELCR H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Event control Peripheral modules Timer event input control Peripheral timer modules ELSR0 to ELSR32 ELOPA ELOPB ELOPC PGR1, PGR2 PGC1, PGC2 Port event input/output control Port 3 or port 6 PDBF1, PDBF2 PEL0 to PEL3 ELTMCR Event-generation timer Event signal 1 ELTMSA Event signal 2 ELTMSB Event signal 3 Event signal 4 ELTMDR ELTMCNT Figure 12.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 12.2 Register Descriptions The ELC has the following registers.
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Section 12 Event Link Controller 12.2.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 12.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 12.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 12 Event Link Controller ELSn7 to ELSn0 Bit Value (Signal Number) Name of Event Signal to Set ELSR 00111001 (H'39) CPG backup start 00111010 (H'3A) WDT increment 00111100 (H'3C) Timer RE interval (week, day, hour, minute, or second) 00111101 (H'3D) DTC transfer end 00111110 (H'3E) Transmit-buffer empty in IIC2/SSU 00111111 (H'3F) Transmit end in IIC2/SSU 01000000 (H'40) Receive-buffer full in IIC2/SSU 01000001 (
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Section 12 Event Link Controller 12.2.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Event Link Option Setting Register A (ELOPA) Address: H'FF06B5 Bit: b7 b6 b5 TMRAM[2:1] Value after reset: 1 1 b4 b3 TMRBM[2:1] 1 1 b2 b1 TMRCM[2:1] 1 b0 TMRD1M[2:1] 1 1 1 Bit Symbol Bit Name Description R/W 7 TMRAM [2:1] Timer RA operation select 00: Timer starts counting. R/W 6 01: Timer counts events. 10: Setting prohibited. 11: Events disabled.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 12.2.4 Event Link Option Setting Register B (ELOPB) Address: H'FF06B6 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 TMRD2M[2:1] ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 1 1 1 1 1 1 1 1 Bit Symbol Bit Name 7, 6 TMRD2M Timer RD_0 [2:1] channel 1 operation select Description R/W 00: Timer starts counting. R/W 01: Timer counts events. 10: Timer performs input-capture operation.
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Section 12 Event Link Controller 12.2.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port-Group Setting Registers 1 and 2 (PGR1 and PGR2) Address: H'FF06A2, H'FF06A3 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PGRn7 PGRn6 PGRn5 PGRn4 PGRn3 PGRn2 PGRn1 PGRn0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 PGRn7 Port-group setting n7 0: The port bit is not specified as the member of the same group.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 12.2.7 Port-Group Control Registers 1 and 2 (PGC1 and PGC2) Address: H'FF06A6, H'FF06A7 Bit: b7 b6 ⎯ Value after reset: b5 b4 PGCOn[2:0] 1 0 0 0 b3 b2 ⎯ PGCOVEn 1 0 b0 b1 PGCIn[1:0] 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯ 000: 0 is output when the event is input.
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Section 12 Event Link Controller 12.2.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 12.2.9 Event Link Port Setting Registers 0 to 3 (PEL0 to PEL3) Address: H'FF06AD to H'FF06B0 Bit: b7 b6 ⎯ Value after reset: b5 b4 PSMn[1:0] 1 0 b3 b2 PSPn[4:3] 0 0 b1 b0 PSPn[2:0] 0 0 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is read as 1. The write value should be 1.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 12.2.10 Event-Generation Timer Control Register (ELTMCR) Address: H'FF06B8 Bit: b7 b6 b5 b4 TMRSTR ⎯ ⎯ ⎯ 0 1 1 1 Value after reset: b3 b2 0 0 b1 b0 CLSRS[3:0] 0 0 Bit Symbol Bit Name Description R/W 7 TMRSTR Timer count start 0: Counter is stopped. R/W 1: Counter is incremented. 6 to 4 ⎯ Reserved These bits are read as 1. The write value should ⎯ be 1.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 12.2.
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Section 12 Event Link Controller Bit Symbol 3 to 0 C0CLS[3:0]* Bit Name H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Description R/W Channel 0 event- 0000: Clock source φELC/1 generation 0001: Clock source φELC/2 interval select 0010: Clock source φELC/4 R/W 0011: Clock source φELC/8 0100: Clock source φELC/16 0101: Clock source φELC/32 0110: Clock source φELC/64 0111: Clock source φELC/128 1000: Clock source φELC/256 (initial value) 1001: Clock source φELC/512 1010: Cloc
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 12.2.
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Section 12 Event Link Controller Bit Symbol 3 to 0 C2CLS[3:0]* Bit Name H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Description R/W Channel 2 0000: Clock source φELC/1 event0001: Clock source φELC/2 generation interval select 0010: Clock source φELC/4 0011: Clock source φELC/8 R/W 0100: Clock source φELC/16 0101: Clock source φELC/32 0110: Clock source φELC/64 0111: Clock source φELC/128 1000: Clock source φELC/256 (initial value) 1001: Clock source φELC/512 1010: Clock
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 12.2.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 12.2.14 ELC Timer Counter (ELTMCNT) Address: H'FF06C0 Bit: Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ELTMCNT is a 16-bit readable/writable up-counter. To select the input clock signal to be supplied to the counter, use the CLSRS[3:0] bits in ELTMCR.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 12.3 Operation 12.3.1 Relation between Interrupt Processing and Event Linking The modules incorporated in this LSI are provided with the interrupt request status flags and the bits to enable/disable these interrupt requests. When an interrupt request is generated in a module, the corresponding interrupt request status flag is set.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 12.4 Operations of Modules when Event is Input Module Operations when Event is Input Timer RA Timer RB Each timer operates differently depending on the setting of the relevant event link option setting register as below. Timer RC • Starts counting when an event signal is input. Timer RD • Counts the input events. Timer RG • Performs input-capture operation when an event is input.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 12.3.3 Section 12 Event Link Controller Operation of Peripheral Timer Modules When Event is Input Three different operations are performed depending on the ELOP settings when an event is input. • Counting-Start Operation When an event is input, the timer starts counting, which sets the count start bit* in each timer control register to 1. An event that is input while the count start bit is 1 is invalid.
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Section 12 Event Link Controller 12.3.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Port Operation upon Event Input and Event Generation The port operation to be performed upon event input to the port can be set and the operation causing the port to generate an event can be set. (1) Single-Ports and Port-Groups There are two event link modes: event link to single-ports and event link to port-groups.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (4) Section 12 Event Link Controller Input Port-Group Operation upon Event Input and Event Generation An input port-group generates an event when the signal value of any one of the external pins connected to the relevant port-group changes. The event-generation condition is specified using the PGC1 and PGC2 registers.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Example of Operation for Single-Port Input Port 3 External pin Port 37 On-chip module Event link Port 36 Port 35 Port 34 Example of Operation for Single-Port Output Port 33 On-chip module Event link Port 32 Port 31 Port 30 Port to which event is connected Figure 12.3 Event Linkage related to Single-Ports Page 394 of 982 REJ09B0465-0300 Rev. 3.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group PDBF External signal PDBF 0 0 0 0 P37 P36 0 0 P35 0 0 P34 0 1 P33 0 0 P32 0 1 P31 0 0 P30 P30 to P33 are specified as an input port-group. Event signal Figure 12.4 Event Linkage related to Input Port-Groups REJ09B0465-0300 Rev. 3.
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Section 12 Event Link Controller (6) Operation of Port Buffer Registers (a) Input Port-Groups H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group When an event is input to an input port-group, the signal value of the external pin of the bit specified as the members of the input port-group is transferred to PDBF. If another event is input to the input port-group in this state, the current PDR value is transferred or not depending on the PGCOVE bit setting in PGC as described below.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group External signal PDBF PDR PDBF PDR P33 1 0 1 1 Port P33 P32 0 0 0 0 P32 P31 1 0 1 1 P31 P30 0 0 0 0 P30 Event signal Note: P30 to P33 are specified as an output port-group. Figure 12.
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Section 12 Event Link Controller 12.3.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Event-Generation Timer The event-generation timer can generate an event at specified interval. The generated event can be connected to another module. The features of the timer are given below. • The interval can be generated using the 16-bit free-running counter.
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Section 12 Event Link Controller H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group φELC ELTMDR φELC/one cycle C C Q D Latch C Q D Latch Q D Latch φELC/32768 cycles ELC timer event n (n = 0 to 3) Channel × selectable frequency (16 counter cycles) Event output x Delay time can be specified using ELTMDR. Figure 12.8 Operation of Event-Generation Timer REJ09B0465-0300 Rev. 3.
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Section 12 Event Link Controller 12.3.7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Procedure for Linking Events The following describes the procedure for linking events. 1. Set the operation of the module to which an event is to be linked. 2. To the ELSRn register corresponding to the module to which an event signal is to be linked, set the number of the event signal. 3.
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Section 13 Timer RA H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 13 Timer RA The timer RA is an 8-bit reload timer with a prescaler. The prescaler and the timer are comprised of a reload register and a counter, respectively. 13.1 Overview • Operating mode: 5 modes Timer mode: Counts internal count sources. Pulse output mode: Counts internal count sources and produces a toggle output in timer underflow. Event counter mode: Counts external events.
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Section 13 Timer RA H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 13.1 shows the timer RA input/output pins. Table 13.1 Pin Configuration Name Abbreviation I/O Function Timer RA input/output TRAIO I/O External event input and pulse input/output Timer RA output TRAO Output Inverted pulse output of TRAIO output 13.
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Section 13 Timer RA H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 13.2.1 Timer RA Control Register (TRACR) Address: H'FF06F0 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ TUNDF TEDGF ⎯ TSTOP TCSTF TSTART 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description 7, 6 ⎯ Reserved These bits are read as 0. The write valued should be 0. ⎯ 5 TUNDF [Setting condition] Timer RA underflow flag • When timer RA underflows from H'00 to H'FF.
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Section 13 Timer RA H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 1 TCSTF Timer RA count status flag 0: Timer RA counting has been stopped. R 1: Timer RA counting is in progress. [Setting condition] • When 1 is written to TSTART and counting is started. • The start of counting after ELOPA of the event link controller is selected counting by timer RA, the specified event is occurred, and the TSTART bit is set to 1.
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Section 13 Timer RA H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 13.2.2 Timer RA I/O Control Register (TRAIOC) Address: H'FF06F1 Bit: b7 b6 b5 TIOGT[1:0] Value after reset: 0 b4 TIPF[1:0] 0 Bit Symbol Bit Name 7, 6 TIOGT[1:0] TRAIO event input control 0 0 b3 b2 b1 b0 TIOSEL TOENA TOPCR TEDGSEL 0 0 0 0 Description R/W 00: Input control is not performed. (Events are always enabled.) R/W 01: Input control is performed.
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Section 13 Timer RA H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description 0 TEDGSEL Input/output • polarity switch • R/W R/W Timer mode This bit should be set to 0. Pulse output mode 0: The initial value of TRAIO output is set at a high level. 1: The initial value of TRAIO output is set at a low level. • Event count mode 0: Counter incremented at the TRAIO input rising edge. The initial value of TRAIO output is set at a low level.
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Section 13 Timer RA H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 13.2.3 Timer RA Mode Register (TRAMR) Address: H'FF06F2 Bit: b7 b6 b4 0 0 0 b3 b2 ⎯ TCK[2:0] TCKCUT Value after reset: b5 0 0 b0 b1 TMOD[2:0] 0 0 0 Bit Symbol Bit Name Description R/W 7 TCKCUT R/W 6 to 4 TCK[2:0] Timer RA count 0: Count source is supplied. source cutoff 1: Count source is cut off.
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Section 13 Timer RA 13.2.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RA Interrupt Enable Status Register (TRAIR) Address: H'FF06F5 Bit: b7 b6 b5 b4 b3 b2 b1 b0 TRAIE TRAIF ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 TRAIE Timer RA 0: Timer RA interrupt requests are disabled. interrupt 1: Timer RA interrupt requests are enabled.
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Section 13 Timer RA H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 13.2.5 Timer RA Prescaler Register (TRAPRE) Address: H'FF06F3 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 TRAPRE consists of a reload register and an 8-bit counter, each with an initial value of H'FF. If a down-count is performed using the count source selected with TRAMR and an underflow occurs, the value of the reload register is loaded to the counter.
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Section 13 Timer RA 13.2.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RA Timer Register (TRATR) Address: H'FF06F4 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 TRATR consists of a reload register and an 8-bit counter, each with an initial value of H'FF. TRATR performs a down-count of the prescaler underflows.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 13.3 Operation 13.3.1 Operations Common to Various Modes (1) Section 13 Timer RA Starting and Stopping Operation Writing the value 1 to the TSTART bit in TRACR starts counting in a set operating mode; writing the value 0 to the TSTART bit stops the counting. The prescaler counts down in the counter clock cycle to be input into the prescaler. The timer counts down using the underflow of the prescaler as a count source.
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Section 13 Timer RA H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Write H'01 to TRAPRE and H'25 to TRATR by a program Count source After a write, reload register is written to after four counts of count source.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 13.3.4 Section 13 Timer RA Event Counter Mode This mode counts external events that are input from the TRAIO pin as a count source. Setting the TMOD[2:0] bits in TRAMR to B'010 activates the event-counter mode operation. By setting the TEDGSEL bit in TRAIOC, it is possible to specify whether counting is to be performed on the rising or falling edge of an input event from the TRAIO pin.
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Section 13 Timer RA H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 0 = Contents of TRATR (upper) and TRAPRE (lower) registers Counter value (hexadecimal) H'FFFF Start measurement. Underflow n Measurement is stopped. Measurement is stopped. Start H'0000 Start Set to 1 by a program. TSTART in TRACR "1" "0" Measurement pulse (TRAIO pin input) "1" "0" Set to 0 by a program. TRAIF in TRAIR "1" "0" Set to 0 by a program. TEDGF in TRACR "1" "0" Set to 0 by a program.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 13.3.6 Section 13 Timer RA Pulse Cycle Measurement Mode This mode measures the cycle of external pulses that are input from the TRAIO pin. Setting the TMOD[2:0] bits in TRAMR to B'100 activates the pulse cycle measurement operation.
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Section 13 Timer RA 13.3.7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operation through an Event Link Using the event link controller (ELC), timer RA can be made to operate in the following ways in relation to events occurring in other modules. (1) Starting Counter Operation The start of counting operations by timer RA can be selected by the ELOPA register of the ELC.
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Section 13 Timer RA H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RA prescaler underflow signal Set to 1 by a program.
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Section 13 Timer RA 13.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Usage Notes 1. The prescaler and timer are read out per byte inside the microcomputer even when they are read out in 16-byte unit. Therefore, the timer value can be updated while those two registers are read out. 2. The TEDGF and TUNDF bits in TRACR used in pulse width and pulse cycle measurement modes assume the value 0 when 0 is written by a program and do not change if 1 is written.
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Section 14 Timer RB H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 14 Timer RB The timer RB is an 8-bit reload timer with an 8-bit prescaler. The prescaler and the timer are each comprised of a reload register and a counter. The timer RB has two reload registers: timer RB primary register and timer RB secondary register. 14.1 Overview • Four operating modes Timer mode: Counts either internal count sources or timer RA underflows.
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Section 14 Timer RB H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 14.1 shows the timer RB input/output pins. Table 14.1 Pin Configuration Name I/O Function TRGB Input External trigger input TRBO Output Successive pulse output or one-shot pulse output 14.
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Section 14 Timer RB H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 14.2.1 Timer RB Control Register (TRBCR) Address: H'FFFFA0 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ ⎯ TSTOP TCSTF TSTART 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 to 3 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯ 2 TSTOP Count forced stop 0: Timer RB counting is continued. R/W 1: Timer RB counting is forcedly stopped.
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Section 14 Timer RB 14.2.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RB One-Shot Control Register (TRBOCR) Address: H'FFFFA1 Bit: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ ⎯ TOSSTF TOSSP TOSST 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 to 3 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯ 2 TOSSTF One-shot status flag 0: Timer RB one-shot function has been stopped.
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Section 14 Timer RB H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • TOSSP bit (one-shot stop) Writing 1 to this bit stops the timer counting. This bit is always read as 0 • TOSST bit (one-shot start) In programmable one-shot generation mode or programmable wait one-shot generation mode, writing 1 to this bit starts the timer counting and one-shot pulse output in synchronization with the count source. This bit is always read as 0. 14.2.
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Section 14 Timer RB H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 0 TOPL Timer RB output level select Programmable Waveform Generation Mode R/W 0: A high-level signal is output in primary period, a low-level signal in secondary period and a lowlevel signal when the timer stops. 1: A low-level signal is output in primary period, a high-level signal in secondary period, and a high-level signal when the timer stops.
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Section 14 Timer RB H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 14.2.4 Timer RB Mode Register (TRBMR) Address: H'FFFFA3 Bit: b7 b6 TCKCUT 0 Value after reset: Bit 7 0 Symbol TCKCUT* 1 1 6 to 4 TCK[2:0]* b5 b4 TCK[2:0] 0 0 b3 b2 TWRC ⎯ 0 0 b1 b0 TMOD[1:0] 0 0 Bit Name Description R/W Count source cutoff 0: Timer RB clock source is supplied. R/W Count source select 000: φ 1: Timer RB clock source is cut off.
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Section 14 Timer RB 14.2.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RB Interrupt Request Status Register (TRBIR) Address: H'FFFFA7 Bit: b7 b6 b5 b4 b3 b2 b1 b0 TRBIE TRBIF ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 TRBIE Interrupt enable 0: Timer RB interrupt requests are disabled. R/W 1: Timer RB interrupt requests are enabled.
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Section 14 Timer RB H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 14.2.6 Timer RB Prescaler Register (TRBPRE) Address: H'FFFFA4 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 TRBPRE is a reload register for the timer RB prescaler. The timer RB prescaler consists of a reload register and an 8-bit counter.
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Section 14 Timer RB 14.2.8 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RB Primary Register (TRBPR) Address: H'FFFFA6 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 TRBPR is an 8-bit reload register that sets the cycle or primary period for the timer RB counter. The timer RB counter consists of two registers, primary and secondary registers, and a counter. The primary register and counter are assigned to the same address.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 14.3 Operation 14.3.1 Timer Mode Section 14 Timer RB The internal clock pulses or timer RA underflows are counted as a count source in timer mode. When an underflow occurs on the timer RB counter, the value of TRBPR is reloaded and counting is continued. TRBOCR and TRBSC are not used in timer mode. A count source is selected with the TCK[2:0] bits in TRBMR.
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Section 14 Timer RB 14.3.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Programmable Waveform Generation Mode This mode alternately reloads and counts values of TRBPR and TRBSC, and produces toggle output from the TRBO pin each time the counter underflows. At the start of counting, this mode counts beginning with the value assigned to TRBPR. TRBOCR is not used when programmable waveform generation mode is used.
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Section 14 Timer RB H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 14.2 shows an operation example of the timer RB in programmable waveform generation mode. Set to 1 by a program. TSTART in TRBCR "1" "0" Count source Timer RB prescaler underflow signal Timer RB secondary reload Timer RB counter H'01 H'00 H'02 Timer RB primary reload H'01 H'00 H'01 H'00 H'02 Set to 0 by a program.
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Section 14 Timer RB 14.3.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Programmable One-Shot Generation Mode This mode outputs one-shot pulses from the TRBO pin, based on either program or external trigger input. When a trigger is generated, beginning with that point in time the timer operates only once for any length of time specified in TRBPR. TRBSC is not used in this mode. In this mode, TRBPRE or TRBPR should not be set to H'00.
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Section 14 Timer RB H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Set to 1 by a program. "1" TSTART in TRBCR "0" Write 1 to TOSST in TRBOCR. Change to 0 at the end of counting. Change to 1 by the TRGB pin input trigger. TOSSTF in TRBOCR TRGB pin Count source Timer RB prescaler underflow signal Start of counting Timer RB counter H'01 Timer RB primary reload H'00 Start of counting H'01 Timer RB primary reload H'00 H'01 Set to 0 by a program.
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Section 14 Timer RB 14.3.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Programmable Wait One-Shot Generation Mode This mode outputs one-shot pulses from the TRBO pin after a fixed amount of time based on either program or external trigger input. When a trigger is generated, beginning with that point in time, pulses are output only once for any length of time set in TRBSC, after any length of time set in TRBPR.
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Section 14 Timer RB H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 14.4 shows an operation example of the timer RB in programmable wait one-shot generation mode. Set to 1 by a program. TSTART in TRBCR "1" "0" Change to 1 by writing 1 to TOSST in TRBOCR or by the TRGB pin input trigger. TOSSTF in TRBOCR Change to 0 at the end of counting.
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Section 14 Timer RB 14.3.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timing at Which Values Take Effect in Prescaler or Counter Depending on TWRC Bit Depending on the value assigned to the TWRC bit in TRBMR, the timing at which the value written to TRBPRE, TRBPR, or TRBSC during timer operation takes effect in the counter can vary.
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Section 14 Timer RB H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (1) TWRC=0 Write H'01 to TRBPRE and H'25 to TRBPR by program. Count source After a writing, data are written to the reload register after 4 cycles of the source for counting have elapsed.
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Section 14 Timer RB 14.3.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TOCNT Settings and Pin State Update Conditions Depending on the TOCNT bit in TRBIOC and the corresponding bit in PMR, the user can select whether the pin is used as a general I/O port or as a specific timer waveform output. In the case of timer mode, however, the pin operates as a general I/O port, irrespective of TOCNT bit settings.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 14.3.7 Section 14 Timer RB Operation through an Event Link Using the event link controller (ELC), timer RB can be made to operate in the following ways in relation to events occurring in other modules. (1) Starting Counter Operation The start of counting operations by timer RB can be selected by the ELOPA register of the ELC.
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Section 14 Timer RB 14.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Usage Notes 1. In programmable one-shot generation mode and programmable wait one-shot generation mode, if the counting is stopped by clearing the TSTART bit in TRBCR to 0, the timer counter holds a count value, and then stops. 2. After 1 is written to the TSTART bit when the counting is stopped, the TCSTF bit remains 0 for the number of cycles of the count source.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 15 Timer RC Section 15 Timer RC Timer RC is a 16-bit timer having output compare and input capture functions. Timer RC can count external events and output pulses with a desired duty cycle using the compare match function between the timer counter and four general registers. Thus, it can be applied to various systems. Note: Timer RC is not supported in H8S/20223, H8S/20203, H8S/20215, and H8S/20235 Groups. 15.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 15.1 summarizes the timer RC functions, and figure 15.1 shows a block diagram of timer RC. Table 15.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Internal clock: φ φ/2 φ/4 φ/8 φ/32 FTIOA/TRGC Clock selection FTIOB Control logic External clock: FTCI FTIOC FTIOD Comparator TRCOI OVF IMFA IMFB IMFC Internal data bus Bus interface TRCADCR TRCDF TRCOER TRCIOR1 TRCIOR0 TRCSR TRCIER TRCCR2 TRCCR1 TRCMR GRD GRC GRB GRA TRCCNT IMFD Figure 15.1 Timer RC Block Diagram Table 15.2 summarizes the timer RC pins. Table 15.
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Section 15 Timer RC 15.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Descriptions The timer RC has the following registers.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.2.1 Timer RC Mode Register (TRCMR) Address: H'FFFF8A Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 CTS ⎯ BUFEB BUFEA PWM2 PWMD PWMC PWMB 0 1 0 0 1 0 0 0 Bit Symbol Bit Name Description R/W 7 CTS Counter start 0: TRCCNT stops counting. R/W 1: TRCCNT starts counting.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 2 PWMD PWM mode D Selects the output mode of the FTIOD pin. R/W 0: Functions in timer mode 1: Functions in PWM mode 1 PWMC PWM mode C Selects the output mode of the FTIOC pin. R/W 0: Functions in timer mode 1: Functions in PWM mode 0 PWMB PWM mode B Selects the output mode of the FTIOB pin. R/W 0: Functions in timer mode 1: Functions in PWM mode 15.2.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 1 3 TOD Timer output 0: Output value is 0* . level setting D 1: Output value is 1*1. R/W 2 TOC Timer output 0: Output value is 0*1. level setting C 1: Output value is 1*1. R/W 1 TOB Timer output 0: Output value is 0*1. level setting B 1: Output value is 1*1. R/W 0 TOA Timer output 0: Output value is 0*1. level setting A 1: Output value is 1*1. R/W Notes: 1.
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Section 15 Timer RC 15.2.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RC Control Register 2 (TRCCR2) Address: H'FFFF90 Bit: b7 TCEG[1:0] Value after reset: 0 b5 b4 b3 b2 b1 b0 CSTP ⎯ ⎯ POLD POLC POLB 0 1 1 0 0 0 b6 0 Bit Symbol Bit Name 7, 6 TCEG[1:0] TRGC input edge select Description R/W 00: A trigger input on TRGC is disabled. R/W 01: The rising edge is selected. 10: The falling edge is selected. 11: Both edges are selected.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.2.4 Timer RC Interrupt Enable Register (TRCIER) Address: H'FFFF8C Bit: b7 b6 b5 b4 b3 b2 b1 b0 OVIE ⎯ ⎯ ⎯ IMIED IMIEC IMIEB IMIEA 0 1 1 1 0 0 0 0 Value after reset: Bit Symbol Bit Name 7 OVIE Timer overflow 0: An interrupt (FOVI) requested by the OVF flag in R/W interrupt TRCSR is disabled. enable 1: An interrupt (FOVI) requested by the OVF flag in TRCSR is enabled.
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Section 15 Timer RC 15.2.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RC Status Register (TRCSR) Address: H'FFFF8D Bit: b7 b6 b5 b4 b3 b2 b1 b0 OVF ⎯ ⎯ ⎯ IMFD IMFC IMFB IMFA Value after reset: 0 1 1 1 0 0 0 0 Bit Symbol Bit Name Description R/W 7 OVF Timer overflow flag 0: TRCCNT has not overflowed. R/W 1: TRCCNT has overflowed. [Setting condition] • When TRCCNT overflows from H'FFFF to H'0000.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 15 Timer RC Bit Symbol Bit Name Description R/W 2 IMFC Input capture/ compare match flag C [Setting conditions] R/W • TRCCNT = GRC when GRC functions as an output compare register. • The TRCCNT value is transferred to GRC by an input capture signal when GRC functions as an input capture register. • TRCCNT = GRC when the PWMC bit is set to 1 or the PWM2 bit to 0 in TRCMR.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 0 IMFA Input capture/ compare match flag A [Setting conditions] R/W • TRCCNT = GRA when GRA functions as an output compare register. • The TRCCNT value is transferred to GRA by an input capture signal when GRA functions as an input capture register. [Clearing condition] • Read IMFA when IMFA = 1, then write 0 in IMFA.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.2.6 Timer RC I/O Control Register 0 (TRCIOR0) Address: H'FFFF8E Bit: Value after reset: b7 b6 ⎯ IOB2 1 0 b5 b4 IOB[1:0] 0 0 b3 b2 ⎯ IOA2 1 0 b1 b0 IOA[1:0] 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯ 6 IOB2 I/O control B2 Selects the GRB function.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description 1, 0 IOA[1:0] I/O control A1 When IOA2 = 0, and A0 00: No output on compare match R/W R/W 01: 0 output to the FTIOA pin on compare match of GRA 10: 1 output to the FTIOA pin on compare match of GRA 11: Toggle output to the FTIOA pin on compare match of GRA When IOA2 = 1, 00: Input capture to GRA at rising edge of the FTIOA pin 01: Input capture to GRA at falling edge of the FT
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.2.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 3 IOC3 I/O control C3 0: GRC is used as GR for the FTIOA pin R/W 1: GRC is used as GR for the FTIOC pin 2 IOC2 I/O control C2 0: GRC functions as an output compare register R/W 1: GRC functions as an input capture register 1, 0 IOC[1:0] I/O control C1 and C0 When IOC3 = 0, R/W 00: No output on compare match 01: 0 output to the FTIOA pin on compare match of GRC
PAGE 483
Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.2.8 Timer RC Output Enable Register (TRCOER) Address: H'FFFF92 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 PTO ⎯ ⎯ ⎯ ED EC EB EA 0 1 1 1 1 1 1 1 Bit Symbol Bit Name Description 7 PTO 0: The ED, EC, EB and EA bits are not set to 1 by R/W the low level input of the TRCOI signal.
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Section 15 Timer RC 15.2.9 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RC Digital Filtering Function Select Register (TRCDF) Address: H'FFFF91 Bit: b7 b6 DFCK[1:0] Value after reset: 0 0 b5 b4 b3 b2 b1 b0 ⎯ DFTRG DFD DFC DFB DFA 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7, 6 DFCK[1:0] Digital filter clock These bits select the clock to be used by the select digital filter.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.2.10 Timer RC A/D Conversion Start Trigger Control Register (TRCADCR) Address: H'FFFF93 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ ADTRGAE ADTRGBE ADTRGCE ADTRGDE 1 1 1 1 0 0 0 0 Bit Symbol Bit Name Description R/W 7 to 4 ⎯ Reserved These bits are read as 1. The write value should be 1.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.2.11 Timer RC Counter (TRCCNT) Address: H'FFFF80 Bit: Value after reset: b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRCCNT is a 16-bit readable/writable up-counter. The input clock is selected by bits CKS2 to CKS0 in TRCCR1. TRCCNT can be cleared to H'0000 through a compare match of GRA by setting the CCLR bit in TRCCR1 to 1.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.2.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Each general register is a 16-bit readable/writable register that can function as either an outputcompare register or an input-capture register. The function is selected by settings in TRCIOR0 and TRCIOR1. When a general register is used as an input-compare register, its value is constantly compared with the TRCCNT value.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.3 Operation Timer RC has the following operating modes. • Timer mode operation Enables output compare and input capture functions by setting the IOA2 to IOA0 and IOB2 to IOB0 bits in TRCIOR0 and the IOC3 to IOC0 and IOD3 to IOD0 bits in TRCIOR1. • PWM mode operation Enables PWM mode operation by setting the PWMD, PWMC, and PWMB bits in TRCMR.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 15.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 15.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Periodic counting operation can be performed when GRA is set as an output compare register and the CCLR bit in TRCCR1 is set to 1. When the counter value matches GRA, TRCCNT is cleared to H'0000, and the IMFA flag in TRCSR is set to 1. If the corresponding IMIEA bit in TRCIER is set to 1, an interrupt request is generated. TRCCNT continues counting from H'0000. Figure 15.3 shows an example of periodic counting.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 15.5 shows an example of toggled output when TRCCNT functions as a free-running counter, and the toggled output is selected for both compare matches A and B. TRCCNT H'FFFF GRA GRB Time H'0000 FTIOA Output toggled FTIOB Output toggled Figure 15.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 15.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group The TRCCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when signal levels are changed on an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD) by specifying the general register as an input capture register. The capture timing can be selected from the rising, falling, or both edges. By using the input-capture function, the width or cycle of a pulse can be measured. Figure 15.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 15.8 shows an example of buffer operation when GRA is set as an input-capture register and GRC is set as the buffer register for GRA. TRCCNT functions as a free-running counter and is captured at both rising and falling edges of the FTIOA signal. Due to the buffer operation, the GRA value is transferred to GRC on an input-capture A and the TRCCNT value is stored in GRA.
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Section 15 Timer RC 15.3.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group PWM Mode Operation In PWM mode, PWM waveforms are generated by using GRA as the cycle register and GRB, GRC, and GRD as duty cycle registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output. In PWM mode, a general register functions as an output compare register automatically.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 15 Timer RC Figure 15.9 shows an example of operation in PWM mode. The output signals go 1 and TRCCNT is cleared on compare match A, and the output signals go 0 on compare match B, C, and D. TRCCNT Counter cleared by compare match A GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 15.9 PWM Mode Example (1) Figure 15.10 shows another example of operation in PWM mode.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 15.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TRCCNT is cleared on compare match A, and the FTIOB pin outputs 1 on compare match B and 0 on compare match A. Due to the buffer operation, the FTIOB output levels are changed and the value of buffer register GRD is transferred to GRB whenever compare match B occurs.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figures 15.12 and 15.13 show examples of the output of PWM waveforms with duty cycles of 0% and 100%. TRCCNT GRB changed GRA GRB GRB changed H'0000 Time Duty cycle 0% FTIOB TRCCNT GRB changed Output levels of FTIOB are not changed when compare matches of cycle register and duty cycle register occur simultaneously.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRCCNT GRB changed GRA GRB GRB changed H'0000 Time Duty cycle 100% FTIOB TRCCNT GRB changed Output levels of FTIOB are not changed when compare matches of cycle register and duty cycle register occur simultaneously. GRA GRB changed GRB changed GRB H'0000 Time Duty cycle 0% FTIOB Output levels of FTIOB are not changed when compare matches of cycle register and duty cycle register occur simultaneously.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.3.3 PWM2 Mode Operation In PWM2 mode, waveforms are output on the FTIOB pin when a compare match occurs on GRB or GRC. GRD functions as a buffer register for GRB by setting the BUFEB bit in TRCMR to 1. The output level of the FTIOB signal is specified by the TOB bit in TRCCR1. When TOB = 0, 1 is output on a compare match of GRC and 0 is output on a compare match of GRB.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Trigger signal FTIOA/TRGC Counter clear signal Input control TRCCNT Compare match signal Comparator GRA Comparator GRB Comparator GRC Compare match signal FTIOB Output control GRD Compare match signal Figure 15.14 Block Diagram in PWM2 Mode φ TRCCNT L GRA L GRD M GRB N H'0000 M Compare match signal Figure 15.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group φ TRCCNT N GRA L GRD M GRB N N+1 H'0000 M Counter clear signal by trigger input Figure 15.16 GRD and GRB Buffer Operating Timing in PWM2 Mode (2) In PWM2 mode, a pulse with arbitrary pulse width and delay time to the TRGC input can be output from the FTIOB pin Figures 15.17 and 15.18 show these examples in PWM2 mode.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group The value of TRCCNT H'FFFF GRA GRB GRC H'0000 Time FTIOA/TRGC FTIOB (Output transformation when TOB = 0) When TOB = 0, the trigger input is ignored while the FTIOB pin is driven high, whereas when TOB = 1, the trigger input is ignored while the FTIOB pin is driven low FTIOB (Output transformation when TOB = 1) GRD A GRB B D C A B C D Figure 15.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group The value of TRCCNT H'FFFF GRA GRB GRC H'0000 Time CTS High FTIOA/TRGC FTIOB (Output transformation when TOB = 0) FTIOB (Output transformation when TOB = 1) Figure 15.19 Example of Stopping Operation of the Counter in PWM2 Mode The following is an example of output operation of the one-shot pulse waveform in PWM2 mode.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group The following is an example of operation when TRCCNT starts counting by the TRGC input and the one-shot pulse waveform is output in PWM2 mode.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.3.4 Digital Filtering Function for Input Capture Inputs Input signals on the FTIOA to FTIOD and TRGC pin can be input via the digital filters. The digital filter includes three latches connected in series and a match detector circuit. The input signals on the FTIOA to FTIOD or TRGC pins are using on the sampling clock specified by the DFCK1 and DFCK0 bits in TRCDF.
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Section 15 Timer RC 15.3.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group A/D Conversion Start Trigger Setting Function Timer RC can generate the A/D conversion start trigger signal on compare matches A, B, C, and D by setting the timer RC A/D conversion start trigger control register (TRCADCR). Figure 15.23 shows an example where the A/D conversion start trigger signal is set to be output on compare matches B and C.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 15.
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Section 15 Timer RC 15.3.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Function of Changing Output Pins for GR With the settings of bits IOC3 and IOD3 in TRCIOR1, pins for outputs of compare match signals for GRC and GRD can be changed from the FTIOC and FTIOD pins to the FTIOA and FTIOB pins. This means that the compare match A signal with the compare match C signal can be output on the FTIOA pin.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 15 Timer RC Figure 15.25 is an example when non-overlapped pulses are output on pins FTIOA and FTIOB.
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Section 15 Timer RC 15.3.7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operation through an Event Link Using the event link controller (ELC), timer RC can be made to operate in the following ways in relation to events occurring in other modules. (1) Staring Counter Operation The start of counting operations by timer RC can be selected by ELOPA of the ELC. When the event specified by ELSR2 occur, the CTS bit in TRCMR is set to 1, which stars counting by timer RC.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.4 Operation Timing 15.4.1 TRCCNT Counting Timing Figure 15.26 shows the TRCCNT count timing when the internal clock source is selected. Figure 15.27 shows the timing when the external clock source is selected. φ Internal clock Rising edge TRCCNT input clock TRCCNT N N+1 N+2 Figure 15.
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Section 15 Timer RC 15.4.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Output Compare Output Timing The compare match signal is generated in the last state in which TRCCNT and GR match (when TRCCNT changes from the matching value to the next value). When the compare match signal is generated, the output value selected in TRCIOR is output on the compare match output pin (FTIOA, FTIOB, FTIOC, or FTIOD).
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.4.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TRCIOR0 and TRCIOR1. Figure 15.29 shows the timing when the falling edge is selected. φ Input capture input Input capture signal N-1 TRCCNT N N+1 N+2 N GRA to GRD Figure 15.29 Input Capture Input Signal Timing 15.4.4 Timing of Counter Clearing by Compare Match Figure 15.
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Section 15 Timer RC 15.4.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Buffer Operation Timing Figures 15.31 and 15.32 show the buffer operation timing. φ Compare match signal N TRCCNT GRC, GRD N+1 M GRA, GRB M Figure 15.31 Buffer Operation Timing (Compare Match) φ Input capture signal TRCCNT GRA, GRB GRC, GRD N M N+1 N N+1 M N Figure 15.32 Buffer Operation Timing (Input Capture) Page 490 of 982 REJ09B0465-0300 Rev. 3.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.4.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) matches TRCCNT, the corresponding IMFA to IMFD flag which is used as output compare register is set to 1. The compare match signal is generated in the last state in which the values match (when TRCCNT is updated from the matching count to the next count).
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Section 15 Timer RC 15.4.7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timing of IMFA to IMFD Setting at Input Capture The corresponding IMFA, IMFB, IMFC, or IMFD flag which functions as a general register is set to 1 when an input capture occurs. Figure 15.34 shows the timing of the IMFA to IMFD flag setting at input capture. φ Input capture signal TRCCNT N GRA to GRD N IMFA to IMFD Figure 15.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.4.8 Timing of Status Flag Clearing When the CPU reads a status flag while it is set to 1, then writes 0 in the status flag, the status flag is cleared. Figure 15.35 shows the status flag clearing timing. TRCSR write cycle T1 T2 φ TRCSR address Address Write signal IMFA to IMFD Figure 15.35 Timing of Status Flag Clearing by CPU REJ09B0465-0300 Rev. 3.
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Section 15 Timer RC 15.4.9 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timing of A/D Conversion Start Trigger Generation on Compare Match Figure 15.36 shows the timing of the A/D conversion start trigger generation on compare match. φ TRCCNT input TRCCNT N GR N N+1 Compare match signal A/D conversion trigger signal Figure 15.36 Timing of A/D Conversion Start Trigger Generation on Compare Match Page 494 of 982 REJ09B0465-0300 Rev. 3.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 15.5 Usage Notes The following types of contention or operation can occur in timer RC operation. 1. When the digital filtering function for input is not in use, the pulse width of the input clock signal and the input capture signal must be at least three system clock (φ) cycles when the CKS2 to CKS0 bits in TRCCR1 = B'0XX or B'10X; shorter pulses will not be detected correctly. 2.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Previous clock New clock Counter clock TRCCNT N N+1 N+2 N+3 The rising edge may occur depending on the timing of changing bits CKS2 to CKS0. In this case, TRCCNT counts up. Figure 15.38 Internal Clock Switching and TRCCNT Operation 5. The TOA to TOD bits in TRCCR1 decide the output value of the FTIO pin until the first compare match occurs.
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Section 15 Timer RC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRCCR1 has been set to H'06. Compare match B and compare match C are used. The FTIOB pin output 1, and is set to the toggle output or the 0 output on compare match B.
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Section 15 Timer RC Page 498 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300 Rev. 3.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 16 Timer RD Section 16 Timer RD This LSI has two units of 16-bit timers (timer RD_0 and timer RD_1), each of which has two channels (one unit for the H8S/20103 and H8S/20115 Groups). Table 16.1 lists the timer RD functions, table 16.2 lists the channel configuration of timer RD, and figure 16.1 is a block diagram of the entire timer RD. Block diagrams of channels 0 and 1 are shown in figures 16.2 and 16.3.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • High-speed access by the internal 16-bit bus 16-bit TRDCNT and GR registers can be accessed in high speed by a 16-bit bus interface • Any initial timer output value can be set • Output of the timer is disabled by external trigger • Eleven interrupt sources Four compare match/input capture interrupts and an overflow interrupt are available for each channel. An underflow interrupt can be set for channel 1.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 16.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 16.2 Channel Configuration of Timer RD Unit Channel Pin Timer RD_0 0 FTIOA0 (Unit 0) FTIOB0 FTIOC0 FTIOD0 1 FTIOA1 FTIOB1 FTIOC1 FTIOD1 Timer RD_1 Shared by channels 0 and 1 TRDOI_0 2 FTIOA2 (Unit 1) FTIOB2 FTIOC2 FTIOD2 3 FTIOA3 FTIOB3 FTIOC3 FTIOD3 Shared by channels 2 and 3 Page 502 of 982 TRDOI_1 REJ09B0465-0300 Rev. 3.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRDOI_0 Channel 0 Interrupt request signal ITDMA0 ITDMB0 ITDMC0 ITDMD0 ITDOV0 ITDUD0 FTIOA0 FTIOB0 FTIOC0 FTIOD0 Control logic FTIOA1 Channel 1 Interrupt request signal ITDMA1 ITDMB1 ITDMC1 ITDMD1 ITDOV1 FTIOB1 FTIOC1 FTIOD1 φ, φ/2, φ/4, φ/8, φ/32 ADTRG TRDSTR TRDMDR TRDOER2 Channel 0 timer Channel 1 timer TRDPMR TRDFCR TRDADCR TRDOER1 TRDOCR Module data bus Figure 16.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group FTIOA0 φ, φ/2, φ/4, φ/8, FTIOB0 FTIOC0 FTIOD0 Clock select φ/32 Control logic ITDMA0 ITDMB0 ITDMC0 ITDMD0 ITDOV0 ITDUD0 Comparator TRDDF_0 POCR_0 TRDIER_0 TRDSR_0 TRDIORC_0 TRDIORA_0 TRDCR_0 GRD_0 GRC_0 GRB_0 GRA_0 TRDCNT_0 TRDOI_0 Module data bus Figure 16.2 Timer RD (Channel 0) Block Diagram Page 504 of 982 REJ09B0465-0300 Rev. 3.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group FTIOA1 φ, φ/2, φ/4, φ/8, FTIOB1 FTIOC1 FTIOD1 Clock select φ/32 Control logic ITDMA1 ITDMB1 ITDMC1 ITDMD1 ITDOV1 Comparator TRDDF_1 POCR_1 TRDIER_1 TRDSR_1 TRDIORC_1 TRDIORA_1 TRDCR_1 GRD_1 GRC_1 GRB_1 GRA_1 TRDCNT_1 TRDOI_0 Module data bus Figure 16.3 Timer RD (Channel 1) Block Diagram REJ09B0465-0300 Rev. 3.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 16.3 summarizes the timer RD pins. Table 16.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2 Section 16 Timer RD Register Descriptions Timer RD has the following registers.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Channel 1 • • • • • • • • • • • • Timer RD control register_1 (TRDCR_1) Timer RD I/O control register A_1 (TRDIORA_1) Timer RD I/O control register C_1 (TRDIORC_1) Timer RD status register_1 (TRDSR_1) Timer RD interrupt enable register_1 (TRDIER_1) PWM mode output level control register_1 (POCR_1) Timer RD digital filtering function select register_1 (TRDDF_1) Timer RD counter_1 (TRDCNT_1) General register A_1 (GRA
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.1 Timer RD Start Register (TRDSTR) Address: H'FFFFD2 Bit: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ CSTPN1 CSTPN0 STR1 STR0 Value after reset: 1 1 1 1 1 1 0 0 Bit Bit Name Description R/W 7 to 4 ⎯ Reserved These bits are read as 1. The write value should be 1.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description 0 STR0 Channel 0 counter 0: TRDCNT_0 stops counting. start 1: TRDCNT_0 starts counting. R/W R/W [Setting conditions] • When 1 is written in STR0 • When the specified event is occurred after ELOPA of the event link controller is selected counting by timer RD_0 for channel 0.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.
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Section 16 Timer RD 16.2.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RD PWM Mode Register (TRDPMR) Address: H'FFFFD4 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ PWMD1 PWMC1 PWMB1 ⎯ PWMD0 PWMC0 PWMB0 1 0 0 0 1 0 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is read as 1. The write value should be 1.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 1, 0 CMD[1:0] Combination 00: Channel 0 and channel 1 operate normally mode 1 and 0 01: Channel 0 and channel 1 are used together to operate in reset synchronous PWM mode R/W 10: Channel 0 and channel 1 are used together to operate in complementary PWM mode (transferred when TRDCNT_0 matches GRA_0) 11: Channel 0 and channel 1 are used together to operate in complementary
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRDCNT_0 TRDCNT_1 Normal phase Normal phase Active level Counter phase Counter phase Initial output Active level Initial output Active level Active level Reset synchronous PWM mode Note: Complementary PWM mode Write H'00 to TRDOCR to start initial outputs after stopping the counter. Figure 16.4 Example of Outputs in Reset Synchronous PWM Mode and Complementary PWM Mode 16.2.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 5 EB1 Master enable 0: FTIOB1 pin output is enabled according to the B1 TRDPMR, TRDFCR, and TRDIORA_1 settings R/W 1: FTIOB1 pin output is disabled regardless of the TRDPMR, TRDFCR, and TRDIORA_1 settings (FTIOB1 pin is operated as an I/O port).
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 2 TOC0 Output level select C0 0: 0 output at the FTIOC0 pin* R/W Output level select B0 • 1 TOB0 1: 1 output at the FTIOC0 pin* R/W In modes other than PWM3 mode 0: 0 output at the FTIOB0 pin* 1: 1 output at the FTIOB0 pin* • In PWM3 mode 0: 1 output at the FTIOB0 pin on GRB_1 compare match and 0 output at the FTIOB0 pin on GRB_0 compare match 1: 0 output at the F
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 0 ADTRGA0E A/D 0: A/D conversion start trigger is not generated by conversion compare match of GRA_0 start trigger A0 1: A/D conversion start trigger is generated by enable compare match of GRA_0 R/W TRDADCR selects the trigger source to start A/D conversion. A/D conversion start trigger is generated by a corresponding compare match. 16.2.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.
PAGE 548
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group GR are 16-bit registers. Timer RD has eight general registers (GR), four for each channel. The GR registers are dual function 16-bit readable/writable registers, functioning as either output compare or input capture registers. Functions can be switched by TRDIORA and TRDIORC. The values in GR and TRDCNT are constantly compared with each other when the GR registers are used as output compare registers.
PAGE 549
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.
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Section 16 Timer RD Bit Symbol 2 to 0 TPSC[2:0] H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Name Description R/W Time 000: Internal clock: count by φ prescaler 2 to 001: Internal clock: count by φ/2 0 010: Internal clock: count by φ/4 R/W 011: Internal clock: count by φ/8 100: Internal clock: count by φ/32 101: External clock: count by FTIOA0 (TCLK) pin input 110: Setting prohibited 111: Reserved (setting prohibited) [Legend] X: Don't care Notes: 1.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 3 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯ 2 IOA2 I/O control A2 Selects the GRA function.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 16 Timer RD • TRDIORC Bit Symbol Bit Name Description 7 IOD3 I/O control D3 Specifies GRD to be used as GR for the FTIOB or FTIOD pin. R/W R/W 0: GRD is used as GR for the FTIOB pin 1: GRD is used as GR for the FTIOD pin 6 IOD2 I/O control D2 Selects the GRD function.
PAGE 554
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description 2 IOC2 I/O control C2 Selects the GRC function.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.13 Timer RD Status Register (TRDSR) Address: H'FFFFC7, H'FFFFCE Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ UDF OVF IMFD IMFC IMFB IMFA 1 1 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7, 6 ⎯ Reserved These bits are read as 1. The write value should be 1. ⎯ 5 UDF* Underflow flag 0: TRDCNT_1 has not underflowed. R/W 1: TRDCNT_1 has underflowed.
PAGE 556
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 2 IMFC Input capture/ [Setting conditions] compare • When TRDCNT = GRC and GRC is functioning match flag C as output compare register • When TRDCNT = GRC while the FTIOC pin operates in PWM mode • When TRDCNT = GRC in PWM3 mode, reset synchronous PWM mode, or complementary PWM mode • When TRDCNT value is transferred to GRC by input capture signal and GRC is functioning
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 16 Timer RD Bit Symbol Bit Name Description R/W 0 IMFA Input capture/ [Setting conditions] compare • When TRDCNT = GRA and GRA is functioning match flag A as output compare register • When TRDCNT = GRA in PWM mode, PWM3 mode, reset synchronous PWM mode, or complementary PWM mode (in reset synchronous PWM mode, however, while TRDCNT_0 = GRA_1 and TRDCNT_0 = GRA_0) • When TRDCNT value is transferred to GRA by input capt
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.14 Timer RD Interrupt Enable Register (TRDIER) Address: H'FFFFC8, H'FFFFCF Bit: Value after reset: Bit Symbol b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ OVIE IMIED IMIEC IMIEB IMIEA 1 1 1 0 0 0 0 0 Bit Name Description R/W 7 to 5 ⎯ Reserved These bits are read as 1. The write value should be 1. ⎯ 4 Overflow interrupt 0: Interrupt requests (OVI) by OVF or UDF flag are enable disabled.
PAGE 559
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.15 PWM Mode Output Level Control Register (POCR) Address: H'FFFFC9, H'FFFFD0 Bit: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ ⎯ POLD POLC POLB Value after reset: 1 1 1 1 1 0 0 0 Bit Bit Name Description R/W 7 to 3 ⎯ Reserved These bits are read as 1. The write value should be 1. ⎯ 2 PWM mode output level control D 0: The output level of FTIOD is active low.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.
PAGE 561
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.2.17 Interface with CPU (1) 16-Bit Register TRDCNT and GR are 16-bit registers. Reading/writing in a 16-bit unit is enabled but disabled in an 8-bit unit since the data bus with the CPU is 16-bit width. These registers must always be accessed in a 16-bit unit. Figure 16.5 shows an example of accessing the 16-bit registers.
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Section 16 Timer RD 16.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operation Timer RD has the following operating modes.
PAGE 563
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • FTIOA0 pin Register Name TRDOER1 Bit Name EA0 STCLK CMD1, CMD0 PWM3 IOA2 to IOA0 Setting values 0 0 00 0 XXX PWM3 mode waveform output 0 0 00 1 001, 01X Timer mode waveform output (output compare function) X 0 00 1 1XX Timer mode (input capture function) X 0 00 1 000 General input port (when the corresponding pin PCR = 0) X 1 XX X 0XX TRDFCR TRDIORA Other than above REJ09B0
PAGE 564
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • FTIOB0 pin Register Name TRDOER1 Bit Name EB0 CMD1, CMD0 Setting values 0 TRDFCR TRDPMR TRDIORA PWM3 PWMB0 IOB2 to IOB0 10, 11 X X XXX Complementary PWM mode waveform output 0 01 X X XXX Reset synchronous PWM mode waveform output 0 00 0 X XXX PWM3 mode waveform output 0 00 1 1 XXX PWM mode waveform output 0 00 1 0 001, 01X Timer mode waveform output (output compare function
PAGE 565
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • FTIOC0 pin Register Name TRDOER1 Bit Name EC0 CMD1, CMD0 Setting values 0 TRDFCR TRDPMR TRDIORC PWM3 PWMC0 IOC2 to IOC0 10, 11 X X XXX Complementary PWM mode waveform output 0 01 X X XXX Reset synchronous PWM mode waveform output 0 00 1 1 XXX PWM mode waveform out 0 00 1 0 001, 01X Timer mode waveform output (output compare function) X 00 1 0 1XX Timer mode (input capture f
PAGE 566
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • FTIOD0 pin Register Name TRDOER1 Bit Name ED0 CMD1, CMD0 Setting values 0 TRDFCR TRDPMR TRDIORC PWM3 PWMD0 IOD2 to IOD0 10, 11 X X XXX Complementary PWM mode waveform output 0 01 X X XXX Reset synchronous PWM mode waveform output 0 00 1 1 XXX PWM mode waveform out 0 00 1 0 001, 01X Timer mode waveform output (output compare function) X 00 1 0 1XX Timer mode (input capture f
PAGE 567
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • FTIOA1 pin Register Name TRDOER1 Bit Name EA1 CMD1, CMD0 PWM3 IOA2 to IOA0 Setting values 0 10, 11 X XXX Complementary PWM mode waveform output 0 01 X XXX Reset synchronous PWM mode waveform output 0 00 1 001, 01X Timer mode waveform output (output compare function) X 00 1 1XX Timer mode (input capture function) X 00 1 000 General input port (when the corresponding pin PCR = 0) TRD
PAGE 568
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • FTIOB1 pin Register Name TRDOER1 Bit Name EB1 CMD1, CMD0 Setting values 0 TRDFCR TRDPMR TRDIORA PWM3 PWMB1 IOB2 to IOB0 10, 11 X X XXX Complementary PWM mode waveform output 0 01 X X XXX Reset synchronous PWM mode waveform output 0 00 1 1 XXX PWM mode waveform out 0 00 1 0 001, 01X Timer mode waveform output (output compare function) X 00 1 0 1XX Timer mode (input capture f
PAGE 569
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • FTIOC1 pin Register Name TRDOER1 Bit Name EC1 CMD1, CMD0 Setting values 0 TRDFCR TRDPMR TRDIORC PWM3 PWMC1 IOC2 to IOC0 10, 11 X X XXX Complementary PWM mode waveform output 0 01 X X XXX Reset synchronous PWM mode waveform output 0 00 1 1 XXX PWM mode waveform out 0 00 1 0 001, 01X Timer mode waveform output (output compare function) X 00 1 0 1XX Timer mode (input capture f
PAGE 570
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • FTIOD1 pin Register Name TRDOER1 Bit Name ED1 CMD1, CMD0 Setting values 0 TRDFCR TRDPMR TRDIORC PWM3 PWMD1 IOD2 to IOD0 10, 11 X X XXX Complementary PWM mode waveform output 0 01 X X XXX Reset synchronous PWM mode waveform output 0 00 1 1 XXX PWM mode waveform out 0 00 1 0 001, 01X Timer mode waveform output (output compare function) X 00 1 0 1XX Timer mode (input capture f
PAGE 571
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.3.1 Counter Operation When one of bits STR0 and STR1 in TRDSTR is set to 1, the TRDCNT counter for the corresponding channel begins counting. TRDCNT can operate as a free-running counter, periodic counter, for example. Figure 16.7 shows an example of the counter operation setting procedure.
PAGE 572
Section 16 Timer RD (1) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Free-Running Count Operation and Periodic Count Operation Immediately after a reset, the TRDCNT counters for channels 0 and 1 are all designated as freerunning counters. When the relevant bit in TRDSTR is set to 1, the corresponding TRDCNT counter starts an increment operation as a free-running counter. When TRDCNT overflows, the OVF flag in TRDSR is set to 1.
PAGE 573
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 16.9 illustrates periodic counter operation. TRDCNT value Counter cleared by GR compare match GR value H'0000 Time STR IMF Figure 16.9 Periodic Counter Operation (2) TRDCNT Count Timing • Internal clock operation A system clock (φ), or four types of clocks (φ/2, φ/4, φ/8, or φ/32) that are generated by dividing the system clock can be selected by bits TPSC2 to TPSC0 in TRDCR. Figure 16.
PAGE 574
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • External clock operation An external clock input pin (TCLK) can be selected by bits TPSC2 to TPSC0 in TRDCR, and a detection edge can be selected by bits CKEG1 and CKEG0. To detect an external clock, the rising edge, falling edge, or both edges can be selected. Figure 16.11 illustrates the detection timing of the rising and falling edges. φ External clock input pin TRDCNT input TRDCNT N-1 N N+1 Figure 16.
PAGE 575
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (1) Examples of Waveform Output Operation Figure 16.13 shows an example of 0 output/1 output. In this example, TRDCNT has been designated as a free-running counter, and settings have been made such that 0 is output by compare match A, and 1 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.
PAGE 576
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRDCNT value GRB GRA Time H'0000 FTIOB Toggle output FTIOA Toggle output Figure 16.14 Example of Toggle Output Operation Output Compare Timing (2) The compare match signal is generated in the last state in which TRDCNT and GR match (when TRDCNT changes from the matching value to the next value).
PAGE 577
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.3.3 Input Capture Function The TRDCNT value can be transferred to GR on detection of the input edge of the input capture/output compare pin (FTIOA, FTIOB, FTIOC, or FTIOD). Rising edge, falling edge, or both edges can be selected as the detected edge. When the input capture function is used, the pulse width or period can be measured. Figure 16.
PAGE 578
Section 16 Timer RD (1) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Example of Input Capture Operation Figure 16.17 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the FTIOA pin input capture input edge, the falling edge has been selected as the FTIOB pin input capture input edge, and counter clearing by GRB input capture has been designated for TRDCNT.
PAGE 579
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) Input Capture Signal Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TRDIOR. Figure 16.18 shows the timing when the rising edge is selected. φ Input capture input Input capture signal TRDCNT N GR N Figure 16.18 Input Capture Signal Timing REJ09B0465-0300 Rev. 3.
PAGE 580
Section 16 Timer RD 16.3.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Synchronous Operation In synchronous operation, the values in a number of TRDCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TRDCNT counters can be cleared simultaneously by making the appropriate setting in TRDCR (synchronous clearing). Synchronous operation enables GR to be increased with respect to a single time base. Figure 16.
PAGE 581
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 16 Timer RD Figure 16.20 shows an example of synchronous operation. In this example, synchronous operation has been selected, FTIOB0 and FTIOB1 have been designated for PWM mode, GRA_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 counter clearing source. The same input clock has been set for the channel 0 and channel 1 counter input clocks.
PAGE 582
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 16.21 shows an example of the PWM mode setting procedure. Table 16.
PAGE 583
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 16 Timer RD Figure 16.22 shows an example of operation in PWM mode. The output signals go to 1 and TRDCNT is reset at compare match A, and the output signals go to 0 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0). TRDCNT value Counter cleared by GRA compare match GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 16.22 Example of PWM Mode Operation (1) REJ09B0465-0300 Rev. 3.
PAGE 584
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 16.23 shows another example of operation in PWM mode. The output signals go to 0 and TRDCNT is reset at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1). TRDCNT value Counter cleared by GRA compare match GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 16.
PAGE 585
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figures 16.24 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 0) and 16.25 (when TOB, TOC, and TOD = 0, POLB, POLC, and POLD = 1) show examples of the output of PWM waveforms with duty cycles of 0% and 100% in PWM mode.
PAGE 586
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRDCNT value GRB rewritten GRA GRB rewritten GRB H'0000 Time FTIOB 0% duty TRDCNT value GRB rewritten When cycle register and duty register compare matches occur simultaneously, duty register compare match has priority.
PAGE 587
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.3.6 Section 16 Timer RD Reset Synchronous PWM Mode Three normal- and counter-phase PWM waveforms are output by combining channels 0 and 1 that one of changing points of waveforms will be common. In reset synchronous PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TRDCNT_0 performs an increment operation. Tables 16.5 and 16.
PAGE 588
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group [1] Clear bit STR0 in TRDSTR to 0 and stop the counter operation of TRDCNT_0. Set reset synchronous PWM mode after TRDCNT_0 stops. Reset synchronous PWM mode Stop counter operation [1] Select counter clock [2] Select counter clearing source [3] Set reset synchronous PWM mode [4] Set TRDCNT [5] Set GR [3] Use bits CCLR2 to CCLR0 in TRDCR to select counter clearing source GRA_0.
PAGE 589
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 16 Timer RD Figures 16.27 and 16.28 show examples of operation in reset synchronous PWM mode. TRDCNT value Counter cleared by GRA compare match GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 16.27 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 1) REJ09B0465-0300 Rev. 3.
PAGE 590
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRDCNT value Counter cleared by GRA compare match GRA_0 GRB_0 GRA_1 GRB_1 H'0000 Time FTIOB0 FTIOD0 FTIOA1 FTIOC1 FTIOB1 FTIOD1 FTIOC0 Figure 16.28 Example of Reset Synchronous PWM Mode Operation (OLS0 = OLS1 = 0) In reset synchronous PWM mode, TRDCNT_0 and TRDCNT_1 perform increment and independent operations, respectively. However, GRA_1 and GRB_1 are separated from TRDCNT_1.
PAGE 591
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.3.7 Section 16 Timer RD Complementary PWM Mode Three PWM waveforms for non-overlapped normal and counter phases are output by combining channels 0 and 1. In complementary PWM mode, the FTIOB0 to FTIOD0 and FTIOA1 to FTIOD1 pins become PWM-output pins automatically. TRDCNT_0 and TRDCNT_1 perform an increment or decrement operation. Tables 16.7 and 16.
PAGE 592
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group [1] Complementary PWM mode Stop counter operation [1] [2] Select counter clock [2] Set complementary PWM mode [3] Set TCNT [4] Set GR [5] [3] [4] Enable waveform output [6] Start counter operation [7] [5] [6] [7] Note: Clear bits STR0 and STR1 in TRDSTR to 0, and stop the counter operation of TRDCNT_0. Stop TRDCNT_0 and TRDCNT_1 and set complementary PWM mode.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) Section 16 Timer RD Examples of Complementary PWM Mode Operation Figure 16.31 shows an example of complementary PWM mode operation. In complementary PWM mode, TRDCNT_0 and TRDCNT_1 perform an increment or decrement operation. When TRDCNT_0 and GRA_0 are compared and their contents match, the counter is decremented. And when TRDCNT_1 underflows, the counter is incremented.
PAGE 594
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 16.32 shows an example of PWM waveform output with 0% duty and 100% duty in complementary PWM mode (for one phase). In this figure, GRB_0 is set to a value equal to or greater than GRA_0 and H'0000. The waveform with a duty cycle of 0% and 100% can be output. When buffer operation is used together, the duty cycles can easily be changed, including the above settings, during operation.
PAGE 595
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group In complementary PWM mode, when the counter switches from up-counter to down-counter or vice versa, TRDCNT_0 and TRDCNT_1 overshoots or undershoots, respectively. In this case, the conditions to set the IMFA flag in channel 0 and the UDF flag in channel 1 differ from usual settings. Also, the transfer conditions in buffer operation differ from usual settings. Such timings are shown in figures 16.33 and 16.34.
PAGE 596
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group When the counter is incremented or decremented, the IMFA flag of channel 0 is set to 1, and when the register is underflowed, the UDF flag of channel 0 is set to 1. After buffer operation has been designated for GR, the value in the buffer registers is transferred to GR when the counter is incremented by compare match A0 or when TRDCNT_1 is underflowed.
PAGE 597
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.3.8 Section 16 Timer RD PWM3 Mode Operation In PWM3 mode, single-phase PWM waveforms can be output using TRDCNT_0. The waveform does not overlap its counter-phase waveform. When the PWM3 mode is selected, the FTIOA0 and FTIOB0 pins are automatically set to output pins for the PWM function using TRDCNT_0 regardless of the TRDPMR value.
PAGE 598
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 16.
PAGE 599
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group PWM mode 3 Select counter clock [1] Select counter clearing source [2] Set PWM mode 3 [3] [1] Select the counter clock with bits TPSC2 to TPSC0 in TRDCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TRDCR. [2] Use bits CCLR2 to CCLR0 in TRDCR to select counter clearing source GRA_0. [3] Select PWM mode 3 with bit PWM3 in TRDFCR.
PAGE 600
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 16.37 is an example when non-overlapped pulses are output on pins FTIOA0 and FTIOB0. In this example, TRDCNT_0 functions as a periodic counter which is cleared on compare match A0 (bits CCLR2 to CCLR0 in TRDCR_0 are set to B'001), and PWM3 mode is selected (bit PWM3 in TRDFCR is cleared to 0). The cycle of the pulse is arbitrary.
PAGE 601
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figures 16.38 and 16.39 show examples of stopping operation of the counter in PWM3 mode, when the CCLR2 to CCLR0 bits in TRDCR are set to clear TRDCNT_0 on GRA_0 compare match. For details on PWM3 mode, see section 16.3.8, PWM3 Mode Operation.
PAGE 602
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 16.40 shows an example of starting and stopping operations of counters in PWM3 mode, when TRDCN1_0 is set to be cleared and stopped on GRA_0 compare match (CCLR2 to CCLR0 = 001, CSTPN0 = 0) and TRDCNT_1 is used as a free-running counter.
PAGE 603
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.3.9 Buffer Operation Buffer operation differs depending on whether GR has been designated for an input capture register or an output compare register, or in reset synchronous PWM mode or complementary PWM mode. Table 16.10 shows the register combinations used in buffer operation. Table 16.
PAGE 604
Section 16 Timer RD (2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group When GR is an Input Capture Register When an input capture occurs, the value in TRDCNT is transferred to GR and the value previously stored in the general register is transferred to the buffer register. This operation is illustrated in figure 16.42. Input capture signal General register Buffer register TRDCNT Figure 16.
PAGE 605
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (6) Example of Buffer Operation Setting Procedure Figure 16.43 shows an example of the buffer operation setting procedure. Buffer operation [1] Designate GR as an input capture register or output compare register by means of TRDIOR. Select GR function [1] [2] Designate GR for buffer operation with bits BFD1, BFC1, BFD0, or BFC0 in TRDMDR.
PAGE 606
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group The timing to transfer data is shown in figure 16.45. TRDCNT value Counter is cleared by GRB compare match GRB H'0250 H'0200 H'0100 H'0000 Time GRC H'0200 H'0100 GRA H'0250 H'0200 H'0200 H'0100 H'0200 FTIOB FTIOA Compare match A Figure 16.44 Example of Buffer Operation (1) (Buffer Operation for Output Compare Register) Page 580 of 982 REJ09B0465-0300 Rev. 3.
PAGE 607
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group φ TRDCNT n n+1 Compare match signal Buffer transfer signal GRC GRA N n N Figure 16.45 Example of Compare Match Timing for Buffer Operation Figure 16.46 shows an operation example in which GRA has been designated as an input capture register, and buffer operation has been designated for GRA and GRC.
PAGE 608
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRDCNT value Counter is cleared by the input capture B H'0180 H'0160 H'0005 H'0000 Time FTIOB FTIOA GRA H'0005 H'0160 GRC H'0005 GRB H'0160 H'0180 Input capture A Figure 16.46 Example of Buffer Operation (2) (Buffer Operation for Input Capture Register) φ FTIO pin Input capture signal TRDCNT n GRA M n n N GRC m M M n n+1 N N+1 Figure 16.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figures 16.48 and 16.49 show the operation examples when buffer operation has been designated for GRB_0 and GRD_0 in complementary PWM mode. These are examples when a PWM waveform of 0% duty is created by using the buffer operation and performing GRD_0 ≥ GRA_0.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRDCNT values GRB_0 (When restored, data will be transferred to the saved location regardless of the CMD1 and CMD0 values) TRDCNT_0 GRA_0 TRDCNT_1 H'0999 H'0000 Time GRB_0 GRD_0 H'0999 GRB_0 H'0999 H'0000 H'0999 H'0000 H'0999 FTIOB0 FTIOD0 Figure 16.49 Buffer Operation (4) (Buffer Operation in Complementary PWM Mode CMD1 =1, CMD0 = 0) Page 584 of 982 REJ09B0465-0300 Rev. 3.
PAGE 611
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.3.10 Timer RD Output Timing The outputs of channels 0 and 1 can be disabled or inverted by the settings of TRDOER1 and TRDOCR and the external level. (1) Output Disable/Enable Timing of Timer RD by TRDOER1 Setting the master enable bit in TRDOER1 to 1 disables the output of timer RD. By setting the PCR and PDR of the corresponding I/O port beforehand, any value can be output. Figure 16.
PAGE 612
Section 16 Timer RD (2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Output Disable Timing of Timer RD by External Trigger When TRDOI is selected for inputs and low level is input to TRDOI, the master enable bit in TRDOER1 is set to 1 and the output of timer RD will be disabled. φ TRDOI TRDOER1 Timer RD output pin 0 1 I/O port Timer RD output Timer RD output I/O port Figure 16.
PAGE 613
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (4) Output Inverse Timing by POCR The output level can be inverted by inverting the POLD, POLC, and POLB bits in POCR in PWM mode. Figure 16.53 shows the timing. T1 T2 φ Address bus POCR address POCR Timer RD output pin Inverted Figure 16.53 Example of Output Inverse Timing of Timer RD by Writing to POCR REJ09B0465-0300 Rev. 3.
PAGE 614
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.3.11 Digital Filtering Function for Input Capture Inputs Input signals on the FTIOA to FTIOD pins can be input via the digital filters. The digital filter includes three latches connected in series and a match detector circuit. The latches operate on the sampling clock specified by bits DFCK1 and DFCK0 in TRDDF and stores an input signal on the FTIOA to FTIOD pins.
PAGE 615
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 16.3.12 Function of Changing Output Pins for GR With the settings of bits IOC3 and IOD3 in TRDIORC, pins for outputs of compare match signals for GRC and GRD can be changed from the FTIOC and FTIOD pins to the FTIOA and FTIOB pins. This means that the compare match A signal ORed with the compare match C signal can be output on the FTIOA pin.
PAGE 616
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 16.56 is an example when non-overlapped pulses are output on pins FTIOA0 and FTIOB0.
PAGE 617
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 16 Timer RD 16.3.13 A/D Conversion Start Trigger Setting Function Timer RD can generate the A/D conversion start trigger signal by setting the timer RD A/D conversion start trigger control register (TRDADCR) or bits ADEG and ADTRG in the timer RD function control register (TRDFCR). Figures 16.58 and 16.59 show examples of the A/D conversion trigger signal generation in complementary PWM mode.
PAGE 618
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 16.60 shows an example where the A/D conversion start trigger signal is generated by compare match. In this case, the TRDADCR register must be set. GRA GRB GRC H'0000 Setting of A/D conversion start trigger ADTRG Figure 16.60 Example of A/D Conversion Trigger Signal Generation by Compare Match Figure 16.61 shows the timing for generating the A/D conversion start trigger by compare match.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 16 Timer RD 16.3.14 Operation by Event Clear Using the event link controller (ELC), timer RD unit 0 can be made to operate in the following ways in relation to events occurring in other modules. Each channel 0 and 1 can be specified independently. (1) Staring Counter Operation The start of counting operations by timer RD can be selected by ELOPA and ELOPB of the ELC.
PAGE 620
Section 16 Timer RD 16.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupt Sources There are three kinds of timer RD interrupt sources; input capture/compare match, overflow, and underflow. An interrupt is requested when the corresponding interrupt request flag is set to 1 while the corresponding interrupt enable bit is set to 1. 16.4.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) IMF Flag Set Timing at Input Capture When an input capture signal is generated, the IMF flag is set to 1 and the value of TRDCNT is simultaneously transferred to corresponding GR. Figure 16.63 shows the timing. φ Input capture signal IMF TRDCNT N GR N Figure 16.63 IMF Flag Set Timing at Input Capture (3) Overflow Flag (OVF) Set Timing The overflow flag is set to 1 when the TRDCNT overflows. Figure 16.
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Section 16 Timer RD 16.4.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Status Flag Clearing Timing The status flag can be cleared by writing 0 after reading 1 from the CPU. Figure 16.65 shows the timing in this case. φ TRDSR address Address WTRDSR (internal write signal) IMF, OVF Figure 16.65 Status Flag Clearing Timing 16.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) Conflict between TRDCNT Write and Clear Operations If a counter clear signal is generated in the T2 state of a TRDCNT write cycle, TRDCNT clearing has priority and the TRDCNT write is not performed. Figure 16.66 shows the timing in this case. TRDCNT write cycle T1 T2 φ TRDCNT address WTRDCNT (internal write signal) Counter clear signal N TRDCNT H'0000 Clearing has priority. Figure 16.
PAGE 624
Section 16 Timer RD (4) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Conflict between GR Write and Compare Match If a compare match occurs in the T2 state of a GR write cycle, GR write has priority and the compare match signal is disabled. Figure 16.68 shows the timing in this case. GR write cycle T1 T2 φ GR address WGR (internal write signal) TRDCNT N GR N N+1 M GR write data Disabled Compare match signal Figure 16.
PAGE 625
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (5) Conflict between TRDCNT Write and Overflow/Underflow If overflow/underflow occurs in the T2 state of a TRDCNT write cycle, TRDCNT write has priority without an increment operation. At this time, the OVF flag is set to 1. Figure 16.69 shows the timing in this case.
PAGE 626
Section 16 Timer RD (6) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Conflict between GR Read and Input Capture If an input capture signal is generated in the T2 state of a GR read cycle, the data that is read will be transferred before input capture transfer. Figure 16.70 shows the timing in this case. GR read cycle T2 T1 φ GR address Internal read signal Input capture signal GR Internal data bus X M X Figure 16.
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Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (7) Conflict between Count Clearing and Increment Operations by Input Capture If an input capture and increment signals are simultaneously generated, count clearing by the input capture operation has priority without an increment operation. The TRDCNT contents before clearing counter are transferred to GR. Figure 16.71 shows the timing in this case.
PAGE 628
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Conflict between GR Write and Input Capture (8) If an input capture signal is generated in the T2 state of a GR write cycle, the input capture operation has priority and the write to GR is not performed. Figure 16.72 shows the timing in this case. GR write cycle T1 T2 φ Address bus GR address WGR (internal write signal) Input capture signal TRDCNT GR N M GR write data Figure 16.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (9) Section 16 Timer RD Notes on Setting Reset Synchronous PWM Mode/Complementary PWM Mode When bits CMD1 and CMD0 in TRDFCR are set, note the following: • Write bits CMD1 and CMD0 while TRDCNT_1 and TRDCNT_0 are halted. • Changing the settings of reset synchronous PWM mode to complementary PWM mode or vice versa is disabled.
PAGE 630
Section 16 Timer RD H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRDOCR has been set to H'06. Compare match B0 and compare match C0 are used. The FTIOB0 pin is in the 1 output state, and is set to the toggle output or the 0 output by compare match B0.
PAGE 631
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 17 Timer RE Section 17 Timer RE Timer RE is a timer that provides a realtime clock function to count time ranging from a second to a week and a compare-match function. Figure 17.1 shows a block diagram of the timer RE. 17.
PAGE 632
Section 17 Timer RE H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TREO pin TRECSR PSC divider TREMIN Clock count control circuit TREHR TREWK Bus interface TRESEC φsub TRECR1 TREIFR TRECR2 Interrupt control circuit Interrupt request Figure 17.1 Block Diagram of Timer RE Table 17.1 shows the timer RE input/output pin. Table 17.1 Pin Configuration Pin Name I/O Function TREO Output Clock or compare-match output Page 606 of 982 REJ09B0465-0300 Rev. 3.
PAGE 633
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 17.2 Section 17 Timer RE Register Descriptions The timer RE has the following registers.
PAGE 634
Section 17 Timer RE 17.2.
PAGE 635
Section 17 Timer RE H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 17.2.
PAGE 636
Section 17 Timer RE 17.2.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RE Hour Data Register (TREHR) Address: H'FFFFAA Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 BSY ⎯ HR11 HR10 HR03 HR02 HR01 HR00 ⎯ 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Bit Symbol Bit Name Description R/W 7 BSY Timer RE busy This bit is set to 1 when the timer RE is updating (calculating) R the values of second, minute, hour, and day-of-week data registers.
PAGE 637
Section 17 Timer RE H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 17.2.4 Timer RE Day-of-Week Data Register (TREWK) Address: H'FFFFAB Bit: Value after reset: b7 b6 b5 b4 b3 BSY ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 0 b2 b1 b0 WK[2:0] ⎯ ⎯ ⎯ Bit Symbol Bit Name Description R/W 7 BSY Timer RE busy This bit is set to 1 when the timer RE is updating R (calculating) the values of second, minute, hour, and dayof-week data registers.
PAGE 638
Section 17 Timer RE 17.2.
PAGE 639
Section 17 Timer RE H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRECR1 controls start/stop and reset of the counter. For the definition of time expression, see figure 17.2. Noon 24-hour count 12-hour count 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 PM 0 (Morning) 1 (Afternoon) 000 (Sunday) TREWK Date changes. 24-hour count 12-hour count PM TREWK 18 19 20 21 22 23 0 1 2 3 ...
PAGE 640
Section 17 Timer RE H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • Output-compare mode Bit Symbol Bit Name Description R/W 7 Counter operation start 0: Stops timer counter operation. R/W TSTART 1: Starts timer counter operation. 6 H12_H24 Operating mode 0 should be written to this bit in output-compare mode. R/W 5 PM a.m./p.m. 0 should be written to this bit in output-compare mode.
PAGE 641
Section 17 Timer RE H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 17.2.6 Timer RE Control Register 2 (TRECR2) Address: H'FFFFAD Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ COMIE WKIE DYIE HRIE MNIE SEIE 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7, 6 ⎯ Reserved These bits are read as 0. The write value should be 0.
PAGE 642
Section 17 Timer RE 17.2.7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RE Interrupt Flag Register (TREIFR) Address: H'FFFFAE Bit: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ COMF WKF DYF HRF MNF SECF Value after reset: 0 0 0 0 0 0 0 0 Bit Bit Name Description R/W 7, 6 ⎯ Reserved These bits are read as 0. The write value should be 0.
PAGE 643
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 17 Timer RE Bit Symbol Bit Name Description R/W 2 HRF Hour periodic interrupt request flag [Setting condition] R/W • Each time TREHR is updated in realtime clock mode. (Occurs every hour) [Clearing conditions] 1 MNF Minute periodic interrupt request flag • When 1 is read from the bit and then 0 is written to the bit.
PAGE 644
Section 17 Timer RE 17.2.8 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RE Clock Source Select Register (TRECSR) Address: H'FFFFAF Bit: b7 b6 ⎯ Value after reset: Bit Symbol 7 ⎯ 6 to 4 RCS[6:4]* 0 2 b5 b4 RCS[6:4] 0 0 0 b3 b2 RCS3 RCS2 1 0 b0 b1 RCS[1:0] 0 0 Bit Name Description R/W Reserved This bit is read as 0. The write value should be 0.
PAGE 645
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 17 Timer RE TRECSR selects clock output, operating mode, and clock source. • RCS6 to RCS4 (clock output select) Selects a clock output from the TREO pin when the TOENA bit in TRECR1 is set to 1. • RCS1 and RCS0 (clock source select) Selects a clock source for output-compare mode. For realtime clock mode, the subclock φsub (32.768 kHz) is selected regardless of the setting of these bits. 17.
PAGE 646
Section 17 Timer RE H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TSTART in TRECR1=0 Timer RE operation is stopped. TCSTF in TRECR1=0? TRERST in TRECR1=1 Timer RE registers and control circuit are reset. TRERST in TRECR1=0 Set TRECSR, TRESEC, TREMIN, TREHR, TREWK, TRECR1, H12_H24, PM, and INT. Set TRECR2. Clock output and clock source are selected and second, minute, hour, day-of-week, operating mode, a.m/p.m, and interrupt source are set. An interrupt source is selected.
PAGE 647
Section 17 Timer RE H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 17.3.3 Data Reading Procedure in Realtime Clock Mode When the seconds, minutes, hours, or day-of-week datum is updated while time data is being read, the data obtained may not be correct, and so the time data must be read again. Figure 17.4 shows an example in which correct data is not obtained. In this example, since only TRESEC is read after data update, about 1-minute inconsistency occurs.
PAGE 648
Section 17 Timer RE 17.3.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operation in Realtime Clock Mode Figure 17.5 shows an example of realtime clock mode operation. 1s Approx. 62.5ms Approx. 62.5ms BSY bit SC12 to SC00 in TRESEC 58 59 MN12 to MN00 in TREMIN 03 HR11 to HR00 in TREHR (Not change) "1" PM in TRECR1 00 04 (Not change) "0" WK[2:0] in TREWK SECF in TREIFR MNF in TREIFR (Not change) "1" Set to 0 by accepting an interrupt request or by a program.
PAGE 649
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 17.4 Section 17 Timer RE Operation of Output Compare Mode Writing 0 to the RCS3 bit in TRECSR sets the timer RE in output compare mode and causes it to operate as a counter provided with an 8-bit compare match function. Four count sources can be selected. When used in output compare mode, the timer RE should be initialized.
PAGE 650
Section 17 Timer RE H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group φ/2 φ/4 φ/8 φsub Output control circuit 1/4 TREO pin RCS[1:0] 1/2 4-bit counter φ/32 8-bit counter Match signal RCS2 Comparison circuit TRESEC Interrupt control circuit Interrupt request TREMIN Internal data bus [Legend] TRESEC: Timer RE second data register/counter data register TREMIN: Timer RE minute data register/compare data register RCS2 to RCS0: Bits 2 to 0 in TRECSR Figure 17.
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Section 17 Timer RE 8-bit counter content H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start counting. Match Value set in TREMIN Match Match H'00 Time Set to 1 by a program. TSTART in TRECR1 "1" "0" TCSTF in TRECR1 "1" "0" Two cycles of the maximum count source Set to 0 by a program. COMF in TREIFR "1" "0" TREO output "H" "L" Output polarity is inverted on a compare match .
PAGE 652
Section 17 Timer RE 17.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupt Sources There are six kinds of timer RE interrupts: week interrupts, day interrupts, hour interrupts, minute interrupts, and second interrupts in realtime clock mode, and compare-match interrupts in output compare mode. Table 17.2 shows the interrupt sources. When using an interrupt, initiate the timer RE last after other registers are set.
PAGE 653
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 17.6 (1) Section 17 Timer RE Usage Notes Starting and Stopping Counting Process The timer RE includes a TSTART bit that directs the start or stop of the counting process, and a TCSTF bit that indicates that the counting process has started or stopped. Setting the TSTART bit to 1 causes the timer RE to start counting and assigns 1 to the TCSTF bit.
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Section 17 Timer RE Page 628 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300 Rev. 3.
PAGE 655
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 18 Timer RG Section 18 Timer RG Timer RG is a 16-bit timer with output compare and input capture functions. Timer RG can count using a number of internal or external clocks and output pulses with a desired duty cycle using the compare match function between the timer counter and two general registers. Timer RG is also able to decode the phase difference between two external clocks and increment.
PAGE 656
Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 18.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Internal clock I/O pin φ/2 φ/4 φ/8 φ/32 TGIOA Clock selection TGIOB Control logic External clock TCLKA TCLKB Comparator Interrupt request OVFG UDFG Internal data bus Bus interface Module data bus TRGIER TRGSR TRGIOR TRGCR TRGCNTCR TRGMDR BRB BRA GRB GRA TRGCNT IMFAG IMFBG Figure 18.1 Timer RG Block Diagram Table 18.2 summarizes the timer RG pins. Table 18.
PAGE 658
Section 18 Timer RG 18.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Descriptions Timer RG has the following registers.
PAGE 659
Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 18.2.1 Timer RG Mode Register (TRGMDR) Address: H'FF0646 Bit: Value after reset: b7 b6 STR ⎯ 0 1 b5 b4 DFCK[1:0] 0 0 b3 b2 b1 b0 DFB DFA MDF PWM 0 0 0 0 Bit Symbol Bit Name Description R/W 7 STR Counter start 0: TRGCNT stops counting. R/W 1: TRGCNT performs counting. 6 ⎯ 5, 4 DFCK[1:0] Digital filter clock select Reserved This bit is read as 1. The write value should be 1.
PAGE 660
Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • MDF bit (Phase counting mode select) When this bit is 0, the counter counts the clock pulses specified with the TPSC2 to TPSC0 bits in TRGCR. When this bit is 1, the counter counts the phases produced by TCLKA and TCLKB as specified in TRGCNTCR. 18.2.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 18.2.3 Timer RG Control Register (TRGCR) Address: H'FF0648 Bit: b7 b6 ⎯ Value after reset: b5 b4 CCLR[1:0] 1 0 b3 b2 CKEG[1:0] 0 0 b0 b1 TPSC[2:0] 0 0 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯ 6, 5 CCLR[1:0] Counter clear source select 00: Disables clearing TRGCNT.
PAGE 662
Section 18 Timer RG 18.2.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RG I/O Control Register (TRGIOR) Address: H'FF0649 Bit: b7 b6 BUFB IOB2 0 0 Value after reset: b5 b4 IOB[1:0] 0 0 b3 b2 BUFA IOA2 0 0 b0 b1 IOA[1:0] 0 0 Bit Symbol Bit Name Description R/W 7 BUFB BRB function select 0: BRB does not function as the GRB buffer register. R/W GRB function select 0: GRB is used as a compare match register.
PAGE 663
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 18 Timer RG Bit Symbol Bit Name Description R/W 3 BUFA BRA function select 0: BRA does not function as the GRA buffer register. R/W GRA function select 0: GRA is used as a compare match register. GRA I/O function select When IOA2 = 0, 2 1, 0 IOA2 IOA[1:0] 1: BRA functions as the GRA buffer. R/W 1: GRA is used as an input capture register. R/W 00: Disables pin output at a compare match.
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Section 18 Timer RG 18.2.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RG Status Register (TRGSR) Address: H'FF064A Bit: Value after reset: Bit Symbol b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ DIRF OVF UDF IMFB IMFA 1 1 1 0 0 0 0 0 Bit Name Description R/W 7 to 5 ⎯ Reserved These bits are read as 1. The write value should be 1. ⎯ 4 DIRF Count direction flag 0: TRGCNT is decremented.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description 0 IMFA Input capture/ [Setting conditions] compare • TRGCNT = GRA when GRA functions as an output match flag A compare register • R/W R/W The TRGCNT value is transferred to GRA by an input capture signal when GRA functions as an input capture register [Clearing condition] 18.2.6 • When the DTC is activated by an IMFA interrupt, and the DISEL bit in MRB of the DTC is 0.
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Section 18 Timer RG 18.2.7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RG Counter (TRGCNT) Address: H'FF0640 Bit: b15 Value after reset: 0 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRGCNT is a 16-bit readable/writable register that performs count operation with an input clock. The input clock is selected by bits TPSC2 to TPSC0 in TRGCR.
PAGE 667
Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 18.2.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group BRA and BRB can be used as buffer registers of GRA and GRB, respectively, by setting BUFA and BUFB in TRGIOR. For example, when GRA is set as an output-compare register and BRA is set as the buffer register for GRA, the value in TRGCNT is sent to GRA whenever compare match A is generated.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 18.3 Operation Timer RG has the following operating modes. • Timer mode (the waveform output function by a compare match, and the input-capture function) • PWM mode • Phase counting mode The TGIOA and TGIOB pins indicate the functions by each register setting.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • TGIOB pin Register Name PMR PCR TRGMDR TRGIOR Bit Name PMR PCR PWM IOB2 to IOB0 Setting values 1 0 Function X 0 001, 01X Timer mode waveform output (output compare function) 0 0 1XX Timer mode (input capture function) 1 X XXX General output port 0 X XXX General input port Other than the above Setting prohibited [Legend] X: Don't care. 18.3.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group [1] Select 0 output, 1 output, or toggle output for compare match output by means of TRGIOR. Output selection Select waveform output mode [1] Set output timing [2] Set PDR [3] Set PMR to 1 [4] Start counting [5] [2] Set the timing for compare match generation in GRA/GRB.
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Section 18 Timer RG (b) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Examples of waveform output operation Figure 18.3 shows an example of 0 output/1 output. In this example, TRGCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (c) Output compare output timing A compare match signal is generated in the final state in which TRGCNT and GR match (the point at which the count value matched by TRGCNT is updated). When a compare match signal is generated, the output value set in TRGIOR is output at the output compare output pin (TGIOA, TGIOB).
PAGE 674
Section 18 Timer RG (2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Input Capture Function The TRGCNT value can be transferred to GR on detection of the input-capture/output-compare pin (TGIOA, TGIOB) input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. The pulse width and cycle period can be measured using the input capture function. (a) Example of setting procedure for input capture operation Figure 18.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (b) Example of input capture operation Figure 18.7 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TGIOA pin input capture input edge, falling edge has been selected as the TGIOB pin input capture input edge, and counter clearing by GRB input capture has been designated for TRGCNT.
PAGE 676
Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group φ Input-capture input Input capture signal TRGCNT N-1 N GRA, GRB N+1 N+2 N Figure 18.8 Input Capture Input Signal Timing 18.3.2 PWM Mode In PWM mode, the PWM waveform is output from the TGIOA output pin by using GRA and GRB as a pair. When an output pin is set for PWM mode, the TRGIOR output setting is ignored.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (1) Section 18 Timer RG Example of PWM Mode Setting Procedure Figure 18.9 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TRGCR. When an external clock is selected, select the external clock edge with bits CKEG1 and CKEG0 in TRGCR. PWM mode Select counter clock [1] [2] Use bits CCLR1 and CCLR0 in TRGCR to select the counter clearing source.
PAGE 678
Section 18 Timer RG (2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Examples of PWM Mode Operation Figure 18.10 shows examples of PWM mode operation. When PWM mode is set, the TGIOA pin is automatically set as an output pin. The TGIOA pin outputs 1 on a GRA compare match and outputs 0 on a GRB compare match. The TGIOB pin always functions as an I/O pin for the relevant port. In the examples shown in the figure, GRA and GRB compare matches are set as the TRGCNT clearing source.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRGCNT value Section 18 Timer RG Counter cleared on compare match A GRA GRB H'0000 Time TGIOA (a) Counter cleared by GRA TRGCNT value Counter cleared on compare match B GRB GRA H'0000 Time TGIOA (b) Counter cleared by GRB Figure 18.10 Example of PWM Mode Operation (1) Figure 18.11 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group TRGCNT value Counter cleared on compare match B GRB GRA H'0000 Time TGIOA GRA write GRA write (a) 0% duty cycle TRGCNT value Counter cleared on compare match A GRA GRB H'0000 Time TGIOA GRB write GRB write (b) 100% duty cycle Figure 18.11 Example of PWM Mode Operation (2) Page 654 of 982 REJ09B0465-0300 Rev. 3.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 18.3.3 Section 18 Timer RG Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs (TCLKA and TCLKB pins) is detected and TRGCNT is incremented/decremented accordingly. When phase counting mode is set, the TCLKA and TCLK pins function as external clock input pins and TRGCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TRGCR.
PAGE 682
Section 18 Timer RG (2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Examples of Phase Counting Mode Operation Figures 18.13 to 18.16 show examples of phase counting mode operation, and tables 18.6 to 18.9 summarize the TRGCNT increment/decrement conditions. Table 18.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 18.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 18.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 18.
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Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Note on Phase Counting Mode (3) In phase counting mode, the phase difference and overlap between TCLKA and TCLKB must be at least 1.5 × φ cycle of the system clock when bits TPSC2 to TPSC0 in TRGCR = B'0XX or B'100, and the pulse width must be at least 3 × φ cycle. Figure 18.17 shows the input clock conditions in phase counting mode.
PAGE 687
Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (1) When GR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the general register. This operation is illustrated in figure 18.18. Compare match signal Buffer register General register Comparator TRGCNT Figure 18.
PAGE 688
Section 18 Timer RG H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figures 18.20 and 18.21 show the timings in buffer operation. φ Input capture signal TRGCNT N GRA GRB M BRA BRB N+1 N N+1 M N Figure 18.20 Buffer Operation Timing (Compare Match) φ Compare match signal TRGCNT N BRA BRB M GRA GRB N N+1 M Figure 18.21 Buffer Operation Timing (Input Capture) Page 662 of 982 REJ09B0465-0300 Rev. 3.
PAGE 689
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 18.3.5 Section 18 Timer RG Operation through an Event Link Using the event link controller (ELC), timer RG can be made to operate in the following ways in relation to events occurring in other modules. (1) Staring Counter Operation The start of counting operations by timer RG can be selected by ELOPC of the ELC. When the event specified by ELSR8 occur, the STR bit in TRGMDR is set to 1, which starts counting by timer RG.
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Section 18 Timer RG 18.3.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Digital Filtering Function for Input Capture Inputs Input signals on the TGIOA and TGIOB pins can be input via the digital filters. The digital filter includes three latches connected in series and a matching detecting circuit. The input signals on the TGIOA and TGIOB pins are operated on the sampling clock specified by the DFCK1 and DFCK0 bits in TRGMDR.
PAGE 691
Section 19 Watchdog Timer (WDT) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 19 Watchdog Timer (WDT) The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 19.1.
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Section 19 Watchdog Timer (WDT) 19.
PAGE 693
Section 19 Watchdog Timer (WDT) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 19.2 Register Descriptions The watchdog timer has the following registers. • • • • • Timer control/status register WD (TCSRWD) Timer counter WD (TCWD) Timer mode register WD (TMWD) Timer interrupt control register WD (TICRWD) Timer interrupt flag register WD (TIFRWD) 19.2.
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Section 19 Watchdog Timer (WDT) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name 3 TMWLOCK Timer mode register WD lockdown Description R/W The TMWD register is write-protected when this bit is 1. Once this bit is set to 1, this bit can be cleared only by a reset. R/W 0: Writing to the TMWD register is enabled. 1: Writing to the TMWD register is disabled.
PAGE 695
Section 19 Watchdog Timer (WDT) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 19.2.3 Timer Mode Register WD (TMWD) Address: H'FFFF99 Bit: b7 b6 b5 b4 ⎯ ⎯ ⎯ ⎯ 1 1 1 1 Value after reset: b3 b2 0 0 b1 b0 0 0 CKS[3:0] Bit Symbol Bit Name Description R/W 7 to 4 ⎯ Reserved These bits are read as 1. The write value should always be 1.
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Section 19 Watchdog Timer (WDT) 19.2.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer Interrupt Control Register WD (TICRWD) Address: H'FFFF9B Bit: b7 Value after reset: 1 b6 INTSEL[1:0] 1 Bit Name b5 b4 b3 b2 b1 b0 IWIE ⎯ ⎯ ⎯ ⎯ ⎯ 0 1 1 1 1 1 Bit Symbol Description R/W 7, 6 INTSEL[1:0] WDT periodic 00: Setting prohibited interrupt 01: An interrupt is generated when the upper two bits condition in TCWD is B'01.
PAGE 697
Section 19 Watchdog Timer (WDT) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 19.2.5 Timer Interrupt Flag Register WD (TIFRWD) Address: H'FFFF9C Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 IWF ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 1 1 1 1 1 1 1 Bit Symbol Bit Name Description R/W 7 IWF WDT periodic interrupt request flag 0: No periodic interrupt request R/W 1: Periodic interrupt request is generated.
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Section 19 Watchdog Timer (WDT) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 19.3 Operation 19.3.1 Watchdog Timer Overflow Reset The watchdog timer is provided with an 8-bit counter. After a reset is released, TCWD starts counting up. When the TCWD count value overflows H'FF, an internal reset signal is generated. Since TCWD is a writable counter, it starts counting from the value set in TCWD.
PAGE 699
Section 19 Watchdog Timer (WDT) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 19.3.2 Watchdog Timer Setting Flow The watchdog timer should be set using the procedure shown in figure 19.3. Reset released Clear MSTWDT in MSTCR1 to 0. After reset is released, the WDT starts counting with φloco/8. [1] Release the WDT from module standby . [1] [2][3]Set TMWD to write-enable. Clear B4WI to 0 and set TCSRWE to 1 in TCSRWD. [4][5]The clock source is changed.
PAGE 700
Section 19 Watchdog Timer (WDT) 19.3.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Watchdog Timer Periodic Interrupt When the INTSEL[1:0] bits in TICRWD are set and the timer WD counter reaches the set value, the IWF bit in TIFRWD is set to 1. At this time, if the IWIE bit in TICRWD is 1, an interrupt request is generated. Figure 19.4 shows the interrupt generation timing when INTSEL is B'01. φ TCWD H'3F H'40 Interrupt request flag setting signal IWF Figure 19.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 19.4 Usage Notes 19.4.1 Notes on System Design Section 19 Watchdog Timer (WDT) While the watchdog timer is a useful function that restores the LSI to normal condition if the system runs erratically for some reason, the watchdog timer may fail to be reset properly in situations such as the perpetuation of an endless loop in a specific programming routine in which a counter setting operation is executed.
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Section 19 Watchdog Timer (WDT) Page 676 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300 Rev. 3.
PAGE 703
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 20 Serial Communication Interface 3 (SCI3, IrDA) Section 20 Serial Communication Interface 3 (SCI3, IrDA) This LSI includes a serial communication interface 3 (SCI3), which has three independent channels. The SCI3 can handle both asynchronous and clocked synchronous serial communication.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Clocked synchronous mode • Data length: 8 bits • Receive error detection: Overrun errors Table 20.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 20 Serial Communication Interface 3 (SCI3, IrDA) Channel Abbreviation Pin Register Register Address Noise Canceler Channel 3 SCI3_3 SMR_3 H'FF0560 Available BRR_3 H'FF0561 SCR3_3 H'FF0562 TDR_3 H'FF0563 SSR_3 H'FF0564 RDR_3 H'FF0565 RSR_3 ⎯ TSR_3 ⎯ SPMR_3 H'FF0566 SCK3_3 RXD_3 TXD_3 Notes: 1. Channel 1 of the SCI3 is used in on-board programming mode by boot mode. 2.
PAGE 706
Section 20 Serial Communication Interface 3 (SCI3, IrDA) SCK3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group External clock Internal clock (φ/64, φ/16, φ/4, φ) Baud rate generator BRC BRR Clock Internal data bus SMR Transmit/receive control circuit SCR3 SSR RXD TXD TSR TDR SPMR RSR RDR Interrupt request (TEI, TXI, RXI, ERI) (1) SCI3 and SCI3_3 External clock SCK3 Baud rate generator Internal clock (φ/64, φ/16, φ/4, φ) BRC BRR Clock SCR3 SSR TSR TDR RSR R
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 20 Serial Communication Interface 3 (SCI3, IrDA) Table 20.2 shows the SCI3 pin configuration. Table 20.
PAGE 708
Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Descriptions The SCI3 has the following registers.
PAGE 709
Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.2.1 Receive Shift Register (RSR) Address: ⎯ Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ RSR is a shift register that is used to receive serial data input from the RXD pin and convert it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 20.2.
PAGE 710
Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Transmit Data Register (TDR) Address: H'FF0553, H'FF055B, H'FF0563 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission.
PAGE 711
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 20 Serial Communication Interface 3 (SCI3, IrDA) Bit Symbol Bit Name Description R/W 4 PM Parity mode (Enabled only when the PE bit is 1 in asynchronous mode) R/W 0: Selects even parity. 1: Selects odd parity. 3 STOP Stop bit length (Enabled only in asynchronous mode) R/W 0: 1 stop bit 1: 2 stop bits 2 MP Multiprocessor mode 0: The multiprocessor communication function is R/W disabled.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Serial Control Register 3 (SCR3) Address: H'FF0552, H'FF055A, H'FF0562 Bit: Value after reset: b7 b6 b5 b4 b3 b2 TIE RIE TE RE MPIE TEIE 0 0 0 0 0 0 b0 b1 CKE[1:0] 0 0 Bit Symbol Bit Name Description R/W 7 TIE Transmit interrupt enable 0: The TXI interrupt request is disabled. R/W 1: The TXI interrupt request is enabled.
PAGE 713
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Name Section 20 Serial Communication Interface 3 (SCI3, IrDA) Bit Symbol Description 1, 0 CKE[1:0] Clock enable 0 Selects the clock source. and 1 Asynchronous mode: R/W R/W 00: On-chip baud rate generator 01: On-chip baud rate generator Outputs a clock of the same frequency as the bit rate from the SCK3 pin. 10: External clock A clock with a frequency 16 times the bit rate should be input from the SCK3 pin.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name 4 FER Section 20 Serial Communication Interface 3 (SCI3, IrDA) Description R/W R/W Framing error [Setting condition] flag • When a framing error occurs in reception [Clearing condition] • 3 PER Parity error flag When the CPU writes 0 after reading FER = 1.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.2.8 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Rate Register (BRR) Address: H'FF0551, H'FF0559, H'FF0561 Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 20.3 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 SMR in asynchronous mode. Table 20.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 20.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) Operating Frequency φ (MHz) 4 4.9152 5 6 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 70 0.03 2 86 0.31 2 88 -0.25 2 106 -0.44 150 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16 300 1 103 0.16 1 127 0.00 1 129 0.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operating Frequency φ (MHz) 10 12 12.888 14 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 177 -0.25 2 212 0.03 2 217 0.08 2 248 -0.17 150 2 129 0.16 2 155 0.16 2 159 0.00 2 181 0.16 300 2 64 0.16 2 77 0.16 2 79 0.00 2 90 0.16 600 1 129 0.16 1 155 0.16 1 159 0.00 1 181 0.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 20.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N φ (MHz) Maximum Bit Rate (bit/s) n N 4 125000 0 0 12 375000 0 0 4.9152 153600 0 0 12.288 384000 0 0 5 156250 0 0 14 437500 0 0 6 187500 0 0 14.7456 460800 0 0 6.144 192000 0 0 16 500000 0 0 7.3728 230400 0 0 17.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 20.5 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) Bit Rate (bit/s) 4 8 10 16 n N n N n N n N 250 2 249 3 124 ⎯ ⎯ 3 249 500 2 124 2 249 ⎯ ⎯ 3 1k 1 249 2 124 ⎯ ⎯ 2.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.2.9 Sampling Mode Register (SPMR) Address: H'FF0556, H'FF055E, H'FF0566 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ ⎯ NFEN ⎯ ⎯ 1 1 1 1 1 0 1 1 Bit Symbol Bit Name Description R/W 7 to 3 ⎯ Reserved These bits are read as 1. The write value should ⎯ be 1.
PAGE 722
Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.2.10 IrDA Control Register (IrCR) Address: H'FF05DE Bit: b7 b6 IrE Value after reset: 0 b5 IrCK[2:0] 0 b3 b2 b1 b0 IrTXINV IrRXINV ⎯ ⎯ 0 0 1 1 b4 0 0 Bit Symbol Bit Name Description R/W 7 IrE IrDA enable 0: The TXD_2/IrTXD and RXD_2/IrRXD pins function as the TXD_2 and RXD_2 pins.
PAGE 723
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 20 Serial Communication Interface 3 (SCI3, IrDA) • IrE bit (IrDA enable) Selects the SCI3_2 I/O pin function between the usual serial function and IrDA function. • IrCK[2:0] bit (IrDA clock select 2 to 0) Sets the high pulse width for IrTXD output pulse encoding when the IrDA function is • IrTXINV bit (IrTX data polarity inversion) Sets to invert the logic level of the IrTXD output.
PAGE 724
Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operation in Asynchronous Mode Figure 20.2 shows the general format for asynchronous communication. One character (or frame) consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full-duplex.
PAGE 725
Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.3.2 SCI3 Initialization Figure 20.4 shows a sample flowchart to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR.
PAGE 726
Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.3.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Data Transmission Figure 20.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2.
PAGE 727
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start transmission [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR [2] Yes Is data transmission continued? No Read TEND flag in SSR Section 20 Serial Communication Interface 3 (SCI3, IrDA) [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0.
PAGE 728
Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.3.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Data Reception Figure 20.7 shows an example of operation for reception in asynchronous mode. In reception, the SCI3 operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
PAGE 729
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 20 Serial Communication Interface 3 (SCI3, IrDA) Table 20.6 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 20.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Receive error processing (Continued on next page) Read RDRF flag in SSR [2] No RDRF = 1 Yes Read receive data in RDR Yes Is data reception continued? [3] [1] Read the OER, PER, and FER flags in SSR to identify the error.
PAGE 731
Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group [4] Receive error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 20.8 Sample Flowchart for Data Reception (Asynchronous Mode) (2) REJ09B0465-0300 Rev. 3.
PAGE 732
Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operation in Clocked Synchronous Mode Figure 20.9 shows the format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.4.3 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Data Transmission Figure 20.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2.
PAGE 734
Section 20 Serial Communication Interface 3 (SCI3, IrDA) Start transmission [1] H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group [1] Read TDRE flag in SSR No TDRE = 1 Yes [2] Write transmit data to TDR [2] Is data transmission continued? Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission.
PAGE 735
Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.4.4 Data Reception (Clocked Synchronous Mode) Figure 20.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronization clock input or output and starts receiving data. 2. The SCI3 stores the receive data in RSR. 3.
PAGE 736
Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start reception [1] [1] Read OER flag in SSR [2] Yes OER = 1 [4] No Overrun error processing (Continued below) [3] Read RDRF flag in SSR [2] No RDRF = 1 [4] Yes Read receive data in RDR Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing.
PAGE 737
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.4.5 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Simultaneous Data Transmission and Reception Figure 20.14 shows a sample flowchart for simultaneous transmit and receive operations. The following procedure should be used for simultaneous data transmit and receive operations.
PAGE 738
Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start transmission/reception [1] [1] Read TDRE flag in SSR No [2] TDRE = 1 Yes Write transmit data to TDR [3] Read OER flag in SSR Yes OER = 1? No [4] Overrun error processing Read RDRF flag in SSR [2] If data is transferred to TDR by the DTC with a transmit data empty interrupt (TXI) request, the TDRE flag is automatically checked and cleared.
PAGE 739
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.5 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data.
PAGE 740
Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) ID transmission cycle = Receiving station specification (MPB = 0) Data transmission cycle = Data transmission to receiving station specified by ID Legend MPB: Multiprocess
PAGE 741
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 20 Serial Communication Interface 3 (SCI3, IrDA) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 [2] Yes Set MPBT bit in SSR Write transmit data to TDR Yes [2] Is data transmission continued? No [3] Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
PAGE 742
Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.5.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Multiprocessor Data Reception Figure 20.17 shows a sample flowchart for multiprocessor data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time.
PAGE 743
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 20 Serial Communication Interface 3 (SCI3, IrDA) [1] [2] Start reception Set MPIE bit in SCR3 to 1 [1] Read OER and FER flags in SSR [2] [3] Yes FER+OER = 1 No Read RDRF flag in SSR [3] No [4] [5] RDRF = 1 Yes Read receive data in RDR No This station’s ID? Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs.
PAGE 744
Section 20 Serial Communication Interface 3 (SCI3, IrDA) [5] H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Receive error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No [A] Framing error processing Clear OER, and FER flags in SSR to 0 Figure 20.17 Sample Flowchart for Multiprocessor Data Reception (2) Page 718 of 982 REJ09B0465-0300 Rev. 3.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 User processing RXI interrupt request is not generated, and RDR retains its state
PAGE 746
Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group IrDA Operation The SCI3_2 provides the IrDA function. If the IrDA function is enabled using the IrE bit in IrCR, the TXD_2 and RXD_2 pins in SCI3_2 are allowed to encode and decode the waveform based on the IrDA Specifications version 1.0 (function as the IrTxD and IrRxD pins)*.
PAGE 747
Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.6.1 Transmission During transmission, the output signals from the SCI3_2 (UART frames) are converted to IR frames using the IrDA interface (see figure 20.20). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCK2 to IrCK0 bits in IrCR.
PAGE 748
Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.6.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group High-Level Pulse Width Selection Table 20.7 shows possible settings for bits IrCK2 to IrCK0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 20.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.7 Noise Canceler Figure 20.21 shows a block diagram of the noise canceler circuit. When the noise canceler function is enabled, the RXD input signal is routed through the noise canceler before being provided internally. The noise canceler consists of three cascaded latches and a match detector.
PAGE 750
Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.8 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupt Requests The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 20.8 shows the interrupt sources. Table 20.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.9 Usage Notes 20.9.1 Break Detection and Processing Section 20 Serial Communication Interface 3 (SCI3, IrDA) When framing error detection is performed, a break can be detected by reading the RXD pin value directly. In a break, the input from the RXD pin becomes all 0s, setting the FER flag, and possibly the PER flag.
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Section 20 Serial Communication Interface 3 (SCI3, IrDA) 20.9.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization.
PAGE 753
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 20.9.5 Section 20 Serial Communication Interface 3 (SCI3, IrDA) Relation between Writes to TDR and TDRE Flag Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data TDR.
PAGE 754
Section 20 Serial Communication Interface 3 (SCI3, IrDA) Page 728 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300 Rev. 3.
PAGE 755
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 21 I2C Bus Interface 2 (IIC2) Section 21 I2C Bus Interface 2 (IIC2) The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 21.1 shows a block diagram of the I2C bus interface 2. Figure 21.2 shows an example of I/O pin connections to external circuits.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Transfer clock generation circuit SCL Transmission/ reception control circuit Output control ICCR1 ICCR2 ICMR Internal data bus Noise canceler ICDRT SDA Output control ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICIER Interrupt generator Interrupt request Figure 21.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Vcc SCL in Vcc SCL SCL SDA SDA SCL out SDA in SCL in SCL out SCL SDA (Master) SCL SDA SDA out SCL in SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 21.2 External Circuit Connections of I/O Pins Table 21.1 summarizes the pin configuration used by the I2C bus interface 2. Table 21.
PAGE 758
Section 21 I2C Bus Interface 2 (IIC2) 21.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Descriptions The IIC2 has the following registers.
PAGE 759
Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 21.2.2 I2C Bus Control Register 1 (ICCR1) Address: H'FF05C8 Bit: Value after reset: Bit 7 6 5 4 Symbol ICE RCVD MST TRS 3 to 0 CKS[3:0] b7 b6 b5 b4 ICE RCVD MST TRS 0 0 0 0 Bit Name b3 b2 0 0 b1 b0 0 0 CKS[3:0] Description R/W I C bus interface 2 enable 0: This module is stopped. (SCL and SDA pins are set to port function.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • CKS[3:0] bits (transfer clock select 3 to 0) These bits should be set according to the necessary transfer rate (see table 21.2) in master mode. In slave mode, these bits are used for reservation of the data setup time in transmit mode. The time is 10 tcyc when CKS3 = 0 and 20 tcyc when CKS3 = 1. Table 21.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 21.2.3 I2C Bus Control Register 2 (ICCR2) Address: H'FF05C9 Bit: Value after reset: Bit Symbol 1 b7 b6 b5 b4 b3 b2 b1 b0 BBSY SCP SDAO SDAOP SCLO ⎯ IICRST ⎯ 0 1 1 1 1 1 0 1 Bit Name 3 Description R/W 2 7 BBSY* * Bus busy 6 SCP*3 Start/stop The SCP bit controls the issue of start/stop R/W condition issue conditions in master mode.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 4 SDAOP SDAO write protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. R/W 3 SCLO SCL output level monitor This bit monitors SCL output level.
PAGE 763
Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group I2C Bus Mode Register (ICMR) 21.2.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • WAIT bit (wait insertion) In master mode with the I2C bus format, this bit selects whether to insert a wait after data transfer except the acknowledge bit. When WAIT is set to 1, after the fall of the clock for the final data bit, low period is extended for two transfer clocks. If WAIT is cleared to 0, data and acknowledge bits are transferred consecutively with no wait inserted.
PAGE 765
Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 21.2.5 I2C Bus Interrupt Enable Register (ICIER) Address: H'FF05CB Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 TIE TEIE RIE NAKIE STIE ACKE ACKBR ACKBT 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description 7 TIE Transmit 0: Transmit data empty interrupt request (TXI) is interrupt enable disabled. R/W R/W 1: Transmit data empty interrupt request (TXI) is enabled.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • TIE bit (transmit interrupt enable) When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). • TEIE bit (transmit end interrupt enable) This bit enables or disables the transmit end interrupt (TEI) at the rising of the ninth clock while the TDRE bit in ICSR is 1. TEI can be canceled by clearing the TEND bit or the TEIE bit to 0.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 21.2.
PAGE 768
Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 5 RDRF Receive data register full flag [Setting condition] R/W • When a receive data is transferred from ICDRS to ICDRR [Clearing conditions] 4 NACKF • When 0 is written in RDRF after reading RDRF = 1 • When ICDRR is read with an instruction • When the DTC transfers data to ICDRR by an RXI interrupt request, and the DTC settings satisfy the fl
PAGE 769
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 21 I2C Bus Interface 2 (IIC2) Bit Symbol Bit Name Description R/W 2 AL_OVE Arbitration lost [Setting conditions] flag/overrun error • If the internal SDA and SDA pin disagree at the flag rise of SCL in master transmit mode • When the SDA pin outputs high in master mode while a start condition is detected • When the final bit is received with the clock synchronous format while RDRF = 1 R/W [Clearing condition] • 1 A
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • AL_OVE bit (arbitration lost flag/overrun error flag) This flag indicates that arbitration was lost in master mode with the I2C bus format and that the final bit has been received while RDRF = 1 with the clock synchronous format.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 21.2.8 I2C Bus Transmit Data Register (ICDRT) Address: H'FF05CE Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data.
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Section 21 I2C Bus Interface 2 (IIC2) 21.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operation The I2C bus interface 2 can communicate either in I2C bus mode or clock synchronous serial mode by setting FS in SAR. 21.3.1 I2C Bus Format Figure 21.3 shows the I2C bus formats. Figure 21.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 21 I2C Bus Interface 2 (IIC2) [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: 21.3.2 Stop condition.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
PAGE 775
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 21.3.3 Section 21 I2C Bus Interface 2 (IIC2) Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, see figures 21.7 and 21.8. The reception procedure and operations in master receive mode are shown below. 1.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 SDA (Master output) SDA (Slave output) 9 1 A A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 21.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A/A SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS ICDRR User processing Data n Data n-1 Data n Data n-1 [5] Read ICDRR after setting RCVD [6] Issue stop condition [7] Read ICDRR, and clear RCVD [8] Set slave receive mode Figure 21.
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Section 21 I2C Bus Interface 2 (IIC2) Slave receive mode SCL (Master output) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Slave transmit mode 9 1 2 3 4 5 6 7 8 9 SDA (Master output) 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS ICDRT ICDRS Data 1 Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Slave receive mode Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 21.
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Section 21 I2C Bus Interface 2 (IIC2) 21.3.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Slave Receive Operation In slave receive mode, the master device outputs the transmit clock and transmit data, and the slave device returns an acknowledge signal. For slave receive mode operation timing, see figures 21.11 and 21.12. The reception procedure and operations in slave receive mode are described below. 1. Set the ICE bit in ICCR1 to 1.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group SCL (Master output) 9 SDA (Master output) 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 SCL (Slave output) SDA (Slave output) A A RDRF ICDRS Data 2 Data 1 ICDRR Data 1 User processing [3] Set ACKBT [3] Read ICDRR [4] Read ICDRR Figure 21.12 Slave Receive Mode Operation Timing (2) 21.3.
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Section 21 I2C Bus Interface 2 (IIC2) (2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Transmit Operation In transmit mode, transmit data is output from SDA in synchronization with the fall of the transfer clock. The transfer clock is output when MST in ICCR1 is 1 and is input when MST is 0. For transmit mode operation timing, see figure 21.14. The transmission procedure and operations in transmit mode are described below. 1. Set the ICE bit in ICCR1 to 1.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (3) Receive Operation In receive mode, data is latched at the rise of the transfer clock. The transfer clock is output when MST in ICCR1 is 1 and is input when MST is 0. For receive mode operation timing, see figure 21.15. The reception procedure and operations in receive mode are described below. 1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS3 to CKS0 bits in ICCR1 to 1 (Initial setting).
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Section 21 I2C Bus Interface 2 (IIC2) 21.3.7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Noise Filter Circuit The signal state on the SCL and SDA pins are internally latched via the noise filter circuit. Figure 21.16 shows a block diagram of the noise filter circuit. The noise filter consists of two cascaded latches and a match detector. The SCL (or SDA) input signal is sampled on the system clock.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 21.3.8 Section 21 I2C Bus Interface 2 (IIC2) Example of Use Flowcharts in respective modes that use the I2C bus interface 2 are shown in figures 21.17 to 21.20. Start Initialize Read BBSY in ICCR2 [1] Test the state of the SCL and SDA lines. [2] Set master transmit mode. [3] Issue the start condition. [1] No BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1. [2] [4] Set the first byte (slave address + R/W) of transmit data.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* [2] Set acknowledge to the transmit device.* [3] Dummy-read ICDRR.* [4] Wait for 1 byte to be received [5] Check whether it is the (last receive - 1). [6] Read the receive data. [7] Set acknowledge of the last byte. Disable continuous reception (RCVD = 1).
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. Read TDRE in ICSR No [5] Wait for the last byte to be transmitted. [3] TDRE=1 ? Yes No [6] Clear the TEND flag . [7] Set slave receive mode. Last byte? Yes [2] Set transmit data for ICDRT (except for the last data).
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? [4] Wait for 1 byte to be received.
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Section 21 I2C Bus Interface 2 (IIC2) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 21.4 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP condition detection, and arbitration lost/overrun error. Table 21.3 shows the contents of each interrupt request. Table 21.
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Section 21 I2C Bus Interface 2 (IIC2) 21.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Synchronous Circuit In master mode, this module has a possibility that high level period may be shortened in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 21.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 21.6 Usage Notes 21.6.1 SCL and SDA pins selected by PMC Section 21 I2C Bus Interface 2 (IIC2) This LSI incorporates the IIC2 and SSU modules, one of which module functions should be selected by the SELICSU bit in ICSUSR. Therefore, when assigning the pin functions using the peripheral function mapping controller (PMC), the SCL and SDA pin functions should be assigned to the P56 and P57 pins when the IIC2 function is selected.
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Section 21 I2C Bus Interface 2 (IIC2) 21.6.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Note on Access to ICE in ICCR1 and IICRST in ICCR2 during I2C Bus Operation Writing 0 to ICE in ICCR1 or 1 to IICRST in ICCR2 while any of the following four conditions during I2C bus operation is satisfied leads to undefined values for BBSY in ICCR2 and STOP in ICSR. 1. This module holds the I2C bus mastership and is in master transmit mode (MST = 1 and TRS = 1 in ICCR1) 2.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 22 Synchronous Serial Communication Unit (SSU) Section 22 Synchronous Serial Communication Unit (SSU) Note: In this section, the synchronous serial communication unit is abbreviated as SSU for convenience. The synchronous serial communication unit (SSU) can handle clocked synchronous serial data communication. Figure 22.1 shows a block diagram of the SSU. Either the SSU or IIC2 incorporated in this LSI can be used at a time.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Internal clock Multiplexer SSCK SSMR SSMR2 SSCRL SCS SSCRH Internal data bus Transmission/ reception control circuit SSER SSSR SSTDR SSO SSI Selector SSTRSR SSRDR Interrupt request (TXI, TEI, RXI, OEI, CEI) Figure 22.1 Block Diagram of SSU Table 22.1 shows the pin configuration of the SSU. Table 22.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 22.2 Register Descriptions The SSU has the following registers. • • • • • • • • • • IIC2/SSU select register (ICSUSR) SS control register H (SSCRH) SS control register L (SSCRL) SS mode register (SSMR) SS mode register 2 (SSMR2) SS enable register (SSER) SS status register (SSSR) SS receive data register (SSRDR) SS transmit data register (SSTDR) SS shift register (SSTRSR) 22.2.
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Section 22 Synchronous Serial Communication Unit (SSU) 22.2.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group SS Control Register H (SSCRH) Address: H'FF05C8 Bit: b7 b6 b5 b4 b3 ⎯ RSSTP MSB ⎯ ⎯ Value after reset: 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯ 6 RSSTP Receive single stop 0: After receiving 1 byte of data, reception continues.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 22.2.3 SS Control Register L (SSCRL) Address: H'FF05C9 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ SOL SOLP ⎯ ⎯ SRES ⎯ 0 1 1 1 1 1 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is read as 0. The write value should be 0. ⎯ 6 ⎯ Reserved This bit is read as 1. The write value should be 1.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • SOL bit (serial data output level setting) Although the value in the last bit of transmit data is retained in the serial data output after the end of transmission, the output level of serial data can be changed by manipulating this bit before or after transmission.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 22.2.
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Section 22 Synchronous Serial Communication Unit (SSU) 22.2.5 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group SS Mode Register 2 (SSMR2) Address: H'FF05CD Bit: Value after reset: b7 b6 BIDE SCKS 0 0 b5 b4 CSS[1:0] 0 b3 b2 b1 b0 SCKOS SOOS CSOS SSUMS 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 BIDE Bidirectional mode enable 0: Normal mode. Communication is performed by using two pins. R/W 1: Bidirectional mode.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 22 Synchronous Serial Communication Unit (SSU) Bit Symbol Bit Name Description R/W 0 SSUMS SSU mode select 0: Clocked synchronous communication mode R/W Data input: SSI pin, Data output: SSO pin 1: Four-line bus communication mode When MSS = 1 in SSCRH and BIDE = 0 in SSMR2: Data input: SSI pin, Data output: SSO pin When MSS = 0 in SSCRH and BIDE = 0 in SSMR2: Data input: SSO pin, Data output: SSI pin When BIDE = 1 in
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • SOOS bit (SSO/SSI pins open-drain output select) Selects whether the serial data output pin is CMOS output or NMOS open-drain output. However, when the SSI output function is allocated to P57, this bit selects between NMOS push-pull output and NMOS open-drain output. The serial data output pin is changed according to the register setting value. For details, see section 22.3.
PAGE 803
Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 22.2.6 SS Enable Register (SSER) Address: H'FF05CB Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 TIE TEIE RIE TE RE ⎯ ⎯ CEIE 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description 7 TIE Transmit interrupt 0: A TXI interrupt request is disabled. enable 1: A TXI interrupt request is enabled.
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Section 22 Synchronous Serial Communication Unit (SSU) 22.2.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 22 Synchronous Serial Communication Unit (SSU) Bit Symbol Bit Name Description R/W 4, 3 ⎯ Reserved These bits are read as 0. The write value should be 0.
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Section 22 Synchronous Serial Communication Unit (SSU) 22.2.8 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group SS Receive Data Register (SSRDR) Address: H'FF05CF Bit: b7 b6 b5 b4 b3 b2 b1 b0 Value after reset: 1 1 1 1 1 1 1 1 SSRDR is an 8-bit register that stores received serial data. When the SSU has received one byte of serial data, it transfers the received serial data from SSTRSR to SSRDR to end receive operation. After this, SSTRSR is receive-enabled.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 22.3 Operation 22.3.1 Transfer Clock Transfer clock can be selected from seven internal clocks and an external clock. When this module is used, the SSCK pin must be selected as a serial clock by setting the SCKS bit in SSMR2 to 1. When the MSS bit in SSCRH is 1, an internal clock is selected and the SSCK pin is in the output state.
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Section 22 Synchronous Serial Communication Unit (SSU) 22.3.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Relationship between Data Input/Output Pin and Shift Register Relationship of connection between the data input/output pin and SSTRSR changes according to a combination of the MSS bit in SSCRH and the SSUMS bit in SSMR2. It also changes by the BIDE bit in SSMR2. Figure 22.3 shows the relationship.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 22.3.4 Section 22 Synchronous Serial Communication Unit (SSU) Communication Modes and Pin Functions The SSU switches functions of the input/output pin in each communication mode according to the settings of the MSS bit in SSCRH and the RE and TE bits in SSER. Table 22.2 shows the relationship between communication modes and the input/output pins.
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Section 22 Synchronous Serial Communication Unit (SSU) 22.3.5 (1) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operation in Clocked Synchronous Communication Mode Initialization in Clocked Synchronous Communication Mode Figure 22.4 shows the initialization in clocked synchronous communication mode. Before transmitting and receiving data, the TE and RE bits in SSER should be cleared to 0, then the SSU should be initialized.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) Serial Data Transmission Figure 22.5 shows an example of the SSU operation for transmission. In serial transmission, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is set as a slave device, it outputs data in synchronized with the input clock.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start Initialization [1] Read TDRE bit in SSSR No TDRE = 1? [1] After reading SSSR and confirming that the TDRE bit is 1, write transmit data in SSTDR. Then the TDRE bit is automatically cleared to 0. Yes Write transmit data in SSTDR [2] Data transmission continued? Yes [2] Determine whether data transmission is continued.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (3) Serial Data Reception Figure 22.7 shows an example of the SSU operation for reception. In serial reception, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a slave device, it inputs data in synchronized with the input clock.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start Initialization [1] Dummy read on SSRDR [2] Last reception? [1] After setting each register in the SSU, dummy read on SSRDR is performed and reception is started. Yes [2] Determine whether the last one byte of data is received. When the last one byte of data is received, set to stop reception after the data is received.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (4) Section 22 Synchronous Serial Communication Unit (SSU) Serial Data Transmission and Reception Data transmission and reception is a combined operation of data transmission and reception which are described before. Transmission and reception is started by writing data in SSTDR. When the eighth clock rises while the TDRE bit is set to 1 or the ORER bit is set to 1, transmission and reception is stopped.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Figure 22.9 shows a sample flowchart for serial transmit and receive operations. Start Initialization [1] Read TDRE in SSSR No TDRE = 1? [1] After reading SSSR and confirming that the TDRE bit is 1, write transmit data in SSTDR. Then the TDRE bit is automatically cleared to 0. Yes Write transmit data in SSTDR [2] No [2] Confirm that the RDRF bit is 1.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 22.3.6 Section 22 Synchronous Serial Communication Unit (SSU) Operation in Four-Line Bus Communication Mode Four-line bus communication mode is a mode which communicates with the four-line bus; a clock line, a data input line, a data output line, and a chip select line. This mode includes bidirectional mode in which the data input line and the data output line function as a single pin.
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Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start Clear TE and RE in SSER to 0 Set SSUMS in SSMR2 to 1 [1] Clear MLS in SSMR to 0 and set CPOS and CPHS, and CKS2 to CKS0 inSSCRH [2] Set SCKS in SSMR2 to 1 and set BIDE, SOOS, CSS1and CSS0, and MSS in SSCRH [1] The MLS bit is cleared to 0 for MSB-first transfer. The clock polarity and phase are set in the CPOS and CPHS bits.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) Section 22 Synchronous Serial Communication Unit (SSU) Serial Data Transmission Figure 22.11 shows an example of the SSU operation for transmission. In serial transmission, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and data. When the SSU is set as a slave device, the SCS pin is in the low-input state and the SSU outputs data in synchronized with the input clock.
PAGE 820
Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (1) When CPOS = 0 and CPHS = 0: SCS (output) (High impedance) SSCK SSO Bit 7 Bit 6 Bit 0 Bit 7 One frame Bit 6 Bit 0 One frame TDRE TEND LSI operation User processing TXI generated Write data in SSTDR TXI generated TEI generated Write data in SSTDR (2) When CPOS = 0 and CPHS = 1: SCS (output) (High impedance) SSCK Bit 7 SSO Bit 6 Bit 0 One frame Bit 7 B
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (3) Section 22 Synchronous Serial Communication Unit (SSU) Serial Data Reception Figure 22.12 shows an example of the SSU operation for reception. In serial reception, the SSU operates as described below. When the SSU is set as a master device, it outputs a synchronous clock and inputs data. When the SSU is set as a slave device, the SCS pin is in the low-input state and inputs data in synchronized with the input clock.
PAGE 822
Section 22 Synchronous Serial Communication Unit (SSU) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (1) When CPOS = 0 and CPHS = 0: SCS (output) (High impedance) SSCK SSI Bit 7 Bit 0 Bit 7 One frame Bit 0 Bit 7 Bit 0 One frame RDRF RSSTP RXI generated LSI operation User processing Dummy read on SSRDR RXI generated Read data in SSRDR Set RSSTP to 1 RXI generated Read data in SSRDR (2) When CPOS = 0 and CPHS = 1: SCS (output) (High impedance) SSCK Bit 7 SS
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 22.3.7 Section 22 Synchronous Serial Communication Unit (SSU) SCS Pin Control and Arbitration When the SSUMS bit in SSMR2 is set to 1 and the CSS1 bit is set to 1, the MSS bit in SSCRH is set to 1 and then the arbitration of the SCS pin is checked before starting serial transfer. If the SSU detects that the synchronized internal SCS pin goes low in this period, the CE bit in SSSR is set and the MSS bit in SSCRH is cleared.
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Section 22 Synchronous Serial Communication Unit (SSU) 22.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupt Requests The SSU has five interrupt requests: transmit data empty, transmit end, receive data full, overrun error, and conflict error. Since these interrupt requests are assigned to the common vector address, interrupt sources must be determined by flags. Table 22.3 lists the interrupt requests. Table 22.
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Section 23 Hardware LIN H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 23 Hardware LIN The hardware LIN works in cooperation with timer RA and SCI3_1 to provide LIN communications. 23.1 Overview • Master mode Generates Sync Break. Detects bus conflicts. • Slave mode Detects Sync Break. Measures Sync Field. Controls Sync Break and Sync Field signal inputs to SCI3_1. Detects bus conflicts. Figure 23.1 shows a block diagram of the hardware LIN interface.
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Section 23 Hardware LIN H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 23.1 shows the hardware LIN pins. Table 23.1 Pin Configuration Pin Symbol I/O Description RXD Input Receive-data input to the hardware LIN TXD Output Transmit-data output from the hardware LIN 23.2 Register Configuration The hardware LIN interface has the following registers. • LIN control register (LINCR) • LIN status register (LINST) 23.2.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 23 Hardware LIN Bit Symbol Bit Name Description R/W 4 LSTART Sync Break detection start 0: Don't care. R/W RXD input status flag 0: Indicates that RXD input has been enabled. 3 RXDSF 1: Enables timer RA input and disables RXD input. R 1: Indicates that RXD input has been disabled. 2 BCIE Bus conflict 0: Disables a bus conflict detection interrupt. detection 1: Enables a bus conflict detection interrupt.
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Section 23 Hardware LIN 23.2.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group LIN Status Register (LINST) Address: H'FF0519 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ B2CLR B1CLR B0CLR BCDCT SBDCT SFDCT 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7, 6 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯ 5 B2CLR BCDCT flag clear The BCDCT flag is cleared when 1 is written to this bit.
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Section 23 Hardware LIN H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 23.3 Operation 23.3.1 Master Mode Figure 23.2 shows the example of hardware LIN interface operation for transmitting the header field in master mode. Figures 23.3 and 23.4 show the flowcharts for header field transmission. The hardware LIN interface operates as follows for header field transmission. 1.
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Section 23 Hardware LIN H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RA Set to timer mode by setting the TMOD[2:0] bits in the TRAMR register to b'000. Timer RA Set the TEDGSEL bit in the TRAIOC register to 1 to set the initial timer pulse output level to low. Timer RA Set the TRAIO pin to RXD by setting the TIOSEL bit in the TRAIOC register to 1. Timer RA Select the count source by setting the TCK[2:0] bits in the TRAMR register.
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Section 23 Hardware LIN H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group A Timer RA Start the timer counter by setting the TSTART bit in the TRACR register to 1. Timer RA Read the count status flag (TCSTF) from the TRACR register. TCSTF = 1? Generate Sync Break by timer RA. After writing 1 to the TSTART bit, reading 1 from the TCSTF flag can be omitted if neither TRAPRE register nor TRATR register of timer RA is read or modified.
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Section 23 Hardware LIN 23.3.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Slave Mode Figure 23.5 shows the example of hardware LIN interface operation for receiving the header field in slave mode. Figures 23.6 to 23.8 show the flowcharts for header field reception. The hardware LIN interface operates as follows for header field reception. 1. When 1 is written to the LSTART bit in LINCR register of the hardware LIN interface, Sync Break detection is enabled. 2.
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Section 23 Hardware LIN H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Sync Break RXD pin "1" "0" RXD input to SCI3_1 "1" "0" RXDSF flag in LINCR Sync Field IDENTIFIER Write 1 to the LSTART bit in LINCR. Automatically cleared to 0 after Sync Field measurement. "1" "0" Write 1 to the B1CLR bit in LINST. SBDCT flag in LINST "1" "0" Measure this period. SFDCT flag in LINST Write 1 to the B0CLR bit in LINST. "1" "0" Timer RA/ "1" HW-LIN interrupt "0" 1. 2. 3. 4. 5.
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Section 23 Hardware LIN H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Timer RA Set to pulse width measurement mode by setting the TMOD[2:0] bits in the TRAMR register to b'011. Timer RA Set the TEDGSEL bit in the TRAIOC register to 0 to measure the low level width of pulses. Timer RA Set the TRAIO pin to RXD by setting the TIOSEL bit in the TRAIOC register to 1. For the hardware LIN function, set the TIOSEL bit in the TRAIOC register to 1.
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Section 23 Hardware LIN H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group A Hardware LIN Enable/disable the interrupts (bus conflict detection, Sync Break detection, and Sync Field measurement end) by setting the BCIE, SBIE, and SFIE bits in the LINCR register. Timer RA Start pulse width measurement by setting the TSTART bit in the TRACR register to 1. Wait until timer RA starts counting. Timer RA Read the count status flag (TCSTF) from the TRACR register.
PAGE 836
Section 23 Hardware LIN H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group B Yes Hardware LIN Read the Sync Field measurement end flag (SFDCT) from the LINST register. SFDCT = 1? No Calculate the hardware LIN Sync Field. The timer RA/HW-LIN interrupt can be used. (When the timer RA counter underflows, the SBDCT flag is set).
PAGE 837
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 23.3.3 Section 23 Hardware LIN Bus Conflict Detection Function The hardware LIN interface can detect bus conflicts if SCI3_1 is enabled for transmission (TE bit in SCR3 register is 1). Figure 23.9 shows the example of hardware LIN interface operation for detecting bus conflicts. TXD pin "1" "0" RXD pin "1" "0" Transfer clock "1" "0" LINE bit in LINCR "1" "0" TE bit in SCR3 register "1" "0" Set to 1 through programming.
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Section 23 Hardware LIN 23.3.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Terminating Hardware LIN Figure 23.10 shows the flowchart for terminating hardware LIN communications. The hardware LIN interface should be terminated at the following timing.
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Section 23 Hardware LIN H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 23.4 Interrupt Requests The hardware LIN interface can request four types of interrupts: Sync Break detection, Sync Break generation end, Sync Field measurement end, and bus conflict detection. All these interrupts are requested as the timer RA interrupt. Table 23.2 describes these interrupt requests. Table 23.
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Section 23 Hardware LIN Page 814 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300 Rev. 3.
PAGE 841
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 24 A/D Converter Section 24 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter (one unit or two units) that allows up to sixteen analog input channels to be selected. Figures 24.1 and 24.2 show the block diagrams of A/D converters unit 1 and unit 2, respectively. The differences between unit 1 and unit 2 are the number of analog input channels and the number of data registers.
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Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Internal data bus Bus interface ADCR ADMR ADCSR ADDR7 ADDR6 ADDR5 ADDR4 ADDR3/CMPVALL ADDR2/CMPVALH AVss ADDR0/CMPR 10-bit D/A ADDR1/CMPCSR AVcc Successive approximations register Module data bus + Comparator Multiplexer AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 Control circuit Sample-and-hold circuit CMPI interrupt signal AAZB ADI interrupt signal Conversion start trigger from t
PAGE 843
Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Internal data bus Bus interface ADCR_2 ADCSR_2 ADMR_2 ADDR3_2/CMPVALL_2 ADDR2_2/CMPVALH_2 AVss ADDR1_2/CMPCSR_2 10-bit D/A ADDR0_2/CMPR_2 AVcc Successive aproximations register Module data bus AN0_2 AN1_2 AN2_2 AN3_2 Multiplexer + Comparator Control circuit Sample-and-hold circuit CMPI interrupt signal AD interrupt signal Conversion start trigger from timer RC or RD ADTRG2 ADTRG1 Figure 24
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Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 24.1 shows the pin configuration of the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. Unit 1 has 12 analog input pins; unit 2 has four analog input pins. Note that the actual number of analog inputs in units 1 and 2 depends on the product group. Table 24.
PAGE 845
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 24.2 Section 24 A/D Converter Register Description The A/D converter has the following registers.
PAGE 846
Section 24 A/D Converter 24.2.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group A/D Data Registers 0 to 7 (ADDR0 to ADDR7) Address: H'FF05E0 to H'FF05EE, H'FF0600 to H'FF0606 Bit: Value after reset: b15 0 b14 0 b13 0 b12 0 b11 0 b10 0 b9 0 b8 0 b7 0 b6 0 b5 b4 b3 b2 b1 b0 − − − − − − 0 0 0 0 0 0 ADDR registers are 16-bit read-only registers which are used to store the results of A/D conversion.
PAGE 847
Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 24.2.2 A/D Control/Status Register (ADCSR) Address: H'FF05F0, H'FF0610 Bit: Value after reset: b7 b6 b5 b4 ADF ADIE ADST ⎯ 0 0 0 0 b3 b2 b1 b0 0 0 CH[3:0] 0 0 Bit Symbol Bit Name Description R/W 7 ADF A/D end flag 0: A/D conversion or comparison is in progress. R/W* 1: A/D conversion or comparison has been completed.
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Section 24 A/D Converter Bit Symbol 3 to 0 CH[3:0] Bit Name H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Description R/W Channel select When SCANE = 1 and SCANS = 0 3 to 0 0000: AN0 0111: AN4 to AN7 0001: AN0 and AN1 R/W 1000: AN8 0010: AN0 to AN2 1001: AN8 and AN9 0011: AN0 to AN3 1010: AN8 to AN10 0100: AN4 1011: AN8 to AN11 0101: AN4 and AN5 11xx: Setting prohibited 0110: AN4 to AN6 When SCANE = 1 and SCANS = 1 0000: AN0 0111: AN0 to AN7 0001: AN0 and AN1 1
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Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group The event link function can be used to set the ADST bit. When the event specified in ELSR10 or ELS11 of the ELC occurs, the corresponding ADST bits (in A/D converter unit 1 or A/D converter unit 2, respectively) are set and the A/D conversion or comparison starts. To select AN0 and AN0_2 as the channels for conversion, specify analog input operation for the pins by setting the PMRA2 and PMRA3 bits. 24.2.
PAGE 850
Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 1 ADSTCLR ADST clear If ADSTCLR is set to 1 in scan mode, the ADST bit R/W is automatically cleared to 0 when A/D conversion of all the selected channels has been completed. 0 EXTRGS External trigger EXTRGS combined with the TRGS1 and TRGS0 select bits selects a trigger signal. For details, see the above description for the TRGS1 and TRGS0 bits.
PAGE 851
Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 24.2.4 A/D Mode Register (ADMR) Address: H'FF05F4, H'FF0614 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ADM1 ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7, 6 ⎯ Reserved These bits are read as 0. The write value should be 0. ⎯ 5 ADM1 A/D converter operating mode selection 0: A/D conversion mode R/W All 0 These bits are read as 0.
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Section 24 A/D Converter 24.2.
PAGE 853
Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group CMP bits and the corresponding analog input channels are shown in table 24.3. Table 24.3 Relationship between CMP Bits and Corresponding Analog Input Channels Unit Unit 1 Unit 2 REJ09B0465-0300 Rev. 3.
PAGE 854
Section 24 A/D Converter 24.2.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Compare Control/Status Register (CMPCSR) Address: H'FF05E2, H'FF0602 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 CMPF CMPIE CMPFC1 CMPFC0 ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 CMPF CMPI interrupt status [Setting condition] R/W If the condition specified by the CMPFC1 or CMPFC0 bit is satisfied when comparison has been completed.
PAGE 855
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 24 A/D Converter Bit Symbol Bit Name Description R/W 5 CMPFC1 CMPI interrupt condition 1 0: Does not generate an interrupt by a comparison result change. R/W 1: In single compare mode: Sets the CMPF bit to 1 if the comparison result of the selected channel changes from 0 to 1. In scan compare mode: Sets the CMPF bit to 1 if the comparison result of any of the selected channels changes from 0 to 1.
PAGE 856
Section 24 A/D Converter 24.2.
PAGE 857
Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group CMPVALL and the lower 2 bits of CMPVALH specify the voltage to be compared. CMPVALH and CMPVALL are assigned to the same addresses as ADDR2 (ADDR2_2) and ADDR3 (ADDR3_2), respectively. CMPVALH and CMPVALL become valid in compare mode. Table 24.4 shows the correspondence between VAL[9:0] setting and the voltage to be compared. Table 24.
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Section 24 A/D Converter 24.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operation The A/D converter operates in two operating modes as shown in table 24.5. In A/D conversion mode, the A/D converter converts the analog input of the selected channel by successive approximation with 10-bit resolution. In compare mode, the analog input of the selected channel is compared with the voltage to be specified. Each operating mode has two operating modes: single mode and scan mode.
PAGE 859
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 24.4 A/D Conversion Mode Operation 24.4.1 Single Mode in A/D Conversion Mode Section 24 A/D Converter In single mode in A/D conversion mode, A/D conversion is to be performed only once on the specified single channel. Operations are as follows. 1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to the software or external trigger input. 2.
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Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Set* ADIE ADST A/D conversion start Set* Set* Clear* Clear* ADF Channel 0 (AN0) operating status Wait for A/D conversion Channel 1 (AN1) operating status Wait for A/D conversion A/D conversion 1 Channel 2 (AN2) operating status Wait for A/D conversion Channel 3 (AN3) operating status Wait for A/D conversion Wait for A/D conversion A/D conversion 2 Wait for A/D conversion ADDR0 ADDR1 Conversion
PAGE 861
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 24.4.2 Section 24 A/D Converter Scan Mode in A/D Conversion Mode In scan mode in A/D conversion mode, A/D conversion is to be performed sequentially on the specified channels: maximum four channels or maximum eight channels. Operations are as follows. 1. When the ADST bit in ADCSR is set to 1 by a software, timer RC, timer RD or external trigger input, A/D conversion starts on the first channel of the channel set.
PAGE 862
Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group A/D conversion is performed sequentially.
PAGE 863
Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 24.5 Compare Mode Operation 24.5.1 Single Mode in Compare Mode In single mode in compare mode, the analog input of one selected channel is compared with the specified voltage. Operations are as follows. The setting of the channel by the CH[3:0] bits in ADCSR is the same as that in A/D conversion mode. 1.
PAGE 864
Section 24 A/D Converter 24.5.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Scan Mode in Comparison Mode In scan mode in comparison mode, the analog input of the selected channels (four or eight maximum) are compared sequentially with the specified voltage. Operations are as follows. 1.
PAGE 865
Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group ADST ADF AN0 Wait for comparison Comparison voltage input Wait for comparison AN1 VAL[9:0] CMP0 in CMPR CMP1 in CMPR Comparison voltage input Wait for comparison Specified voltage Previous comparison result Previous comparison result Comparison result Comparison result Figure 24.6 A/D Converter Operation in Compare Mode (When AN0 to AN2 Channels are Selected in Scan Mode) 24.5.
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Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (1) φ Address (2) Write signal Input sampling timing ADF tD tSPL tCONV Legend: (1) : ADCSR write cycle (2) : ADCSR address : A/D conversion start delay time tD tSPL : Input sampling time tCONV : A/D conversion time Figure 24.7 A/D Conversion Timing Table 24.
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Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 24.7 A/D Conversion Time (Scan Mode) CKS1 CKS0 Conversion Time (State) 1 0 80 1 40 24.5.4 External Trigger Input Timing A/D conversion can be externally triggered. When the EXTRGS, TRGS1, and TRGS0 bits are set to B'001 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge of the ADTRG pin sets the ADST bit in ADCSR to 1, starting A/D conversion.
PAGE 868
Section 24 A/D Converter 24.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Interrupt Source In A/D conversion mode, an A/D conversion end interrupt (ADI) occurs at the end of A/D conversion. Specifically, the ADF bit in ADCSR is set to 1 when A/D conversion is completed; and if the ADIE bit is 1 at this time, the A/D converter generates an ADI interrupt.
PAGE 869
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 24.7 Section 24 A/D Converter A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 24.9).
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Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 24.9 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 24.
PAGE 871
Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 24.8 Usage Notes 24.8.1 Module Standby Mode Setting Operation of the A/D converter can be disabled or enabled using the module standby control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing module standby mode. For details, see section 6, Power-Down Modes. 24.8.
PAGE 872
Section 24 A/D Converter 24.8.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Influences on Absolute Precision Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. 24.8.
PAGE 873
Section 24 A/D Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 24.8.6 Notes on Noise Countermeasures A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN11, AN0_2 to AN3_2) should be connected between AVcc and AVss as shown in figure 24.12. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to AN0 to AN11 or AN0_2 to AN3_2 must be connected to AVss.
PAGE 874
Section 24 A/D Converter 24.8.7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Notes on Analog Input Pins Analog input pins (AN0 to AN11, AN0_2 to AN3_2) are multiplexed with general I/O ports. Accordingly, if the direction of input or output of the general I/O port is changed or the output value of the general I/O port is changed during A/D conversion, the conversion accuracy may be affected.
PAGE 875
Section 25 D/A Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 25 D/A Converter 25.1 • • • • • Features 8-bit resolution Output channels: 2 channels Maximum conversion time of 3 µs (with 20 pF load capacitance) Output voltage of 0 V to AVcc Settable for the module standby mode Internal data bus Bus interface Module data bus AVcc 8-bit DA1 DA0 D/A D A D R 0 D A D R 1 D A C R AVss Control circuit Figure 25.
PAGE 876
Section 25 D/A Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 25.1 shows the input/output pin configuration of the D/A converter. Table 25.1 Pin Configuration Pin Name I/O Function AVcc Input Analog power supply AVss Input Analog ground DA0 Output Channel 0 analog output DA1 Output Channel 1 analog output 25.2 Register Descriptions • D/A data register 0 (DADR0) • D/A data register 1 (DADR1) • D/A control register (DACR) 25.2.
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Section 25 D/A Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 25.2.2 D/A Control Register (DACR) Address: H'FF05D6 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 DAOE1 DAOE0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R/W 7 DAOE1 D/A output enable 1 0: Disables the analog output on channel 1 (DA1). R/W D/A output enable 0 0: Disables the analog output on channel 0 (DA0).
PAGE 878
Section 25 D/A Converter 25.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When DAOE bit in DACR is set to 1, D/A conversion is enabled and the conversion result is output. The operation example of D/A conversion on channel 0 is as follows. Figure 25.2 shows the timing of this operation. 1. Write the conversion data to DADR0. 2.
PAGE 879
Section 25 D/A Converter H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle φ Address DADR0 Conversion data 1 Conversion data 2 DAOE0 DA0 Conversion result 2 Conversion result 1 High-impedance state tDCONV tDCONV Legend: tDCONV: D/A conversion time Figure 25.2 Example of D/A Converter Operation REJ09B0465-0300 Rev. 3.
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Section 25 D/A Converter 25.4 Usage Notes 25.4.1 Setting for Module Stop Mode H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group The module standby control can select to enable/disable the D/A converter operation. The D/A converter does not operate by the initial value of the register. The register can be accessed by releasing the module standby mode. DADR is initialized in module standby. 25.4.
PAGE 881
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 26 Low-Voltage Detection Circuits Section 26 Low-Voltage Detection Circuits This microcontroller includes a low-voltage detection module consisting of three circuits, LVD0, LVD1, and LVD2.
PAGE 882
Section 26 Low-Voltage Detection Circuits 26.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Features • Power-on reset function Monitors the power-supply voltage input to the VCC pin to generate an internal reset signal when power is first supplied. Releases a reset when the power-supply voltage rises above the specified voltage.
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Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group VCC + LVD2 detection voltage - Noise canceler Digital filter Edge detection circuit φloco/8 φloco/4 φloco/2 φloco Reset control circuit LVD2 circuit reset signal Interrupt control circuit LVD2 circuit interrupt signal Figure 26.
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Section 26 Low-Voltage Detection Circuits 26.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Descriptions This module has the following registers.
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Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 26.2.1 Low-Voltage Detection Circuit Control Protect Register (VDCPR) Address: H'FF0628 Bit: Value after reset: 7 6 5 4 3 2 1 0 WRI ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ LDPRC 1 0 0 0 0 0 0 0 Bit Symbol Bit Name Description 7 WRI VDCPR write disable 0: Writing to the VDCPR bit is enabled. R/W W 1: Writing to the VDCPR bit is disabled.
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Section 26 Low-Voltage Detection Circuits 26.2.
PAGE 887
Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 1 VD2MS LVD2 mode select 0: Generates an interrupt request when the voltage reaches Vdet2. R/W 0 VD2RE 1: Generates a reset request when the voltage reaches Vdet2. LVD2 interrupt/ reset request enable This bit is enabled when the VD2E bit is 1. R/W 0: Disables interrupt/reset requests when the specified voltage level is detected.
PAGE 888
Section 26 Low-Voltage Detection Circuits 26.2.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Low-Voltage Detection Circuit 2 Control Register L (LD2CRL) Address: H'FF0623 Bit: b7 b6 b5 b4 b3 b2 b1 b0 VD2E VD2CVS VD2RVS ⎯ ⎯ ⎯ ⎯ ⎯ 0 0 0 0 0 0 0 0 Value after reset: Bit Symbol Bit Name Description R/W 7 VD2E LVD2 circuit enable 0: The LVD2 circuit is not used. (In standby mode) R/W 1: The LVD2 circuit is used.
PAGE 889
Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 26.2.4 Low-Voltage Detection Circuit 1 Control Register H (LD1CRH) Address: H'FF0624 Bit: Value after reset: b7 b6 b5 VD1DF VD1UF 0 0 b4 VD1DFCK[1:0] 0 0 b3 b2 b1 b0 VD1DFS VD1IRCS VD1MS VD1RE 0 0 0 0 Bit Symbol Bit Name Description 7 VD1DF LVD1 power [Setting condition] supply • When the power-supply voltage falls below Vdet1.
PAGE 890
Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit Symbol Bit Name Description R/W 1 VD1MS LVD1 mode 0: Generates an interrupt request when the voltage reaches R/W select Vdet1. 1: Generates a reset request when the voltage reaches Vdet1. 0 VD1RE LVD1 interrupt/ reset request enable This bit is enabled when the VD1E bit is 1. R/W 0: Disables interrupt/reset requests generated when the specified voltage level is detected.
PAGE 891
Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 26.2.5 Low-Voltage Detection Circuit 1 Control Register L (LD1CRL) Address: H'FF0625 Bit: b7 b6 b5 b4 VD1E ⎯ ⎯ ⎯ 0 0 0 0 Value after reset: b3 b2 0 0 b1 b0 0 0 VD1LS[3:0] Bit Symbol Bit Name Description R/W 7 VD1E LVD1 circuit enable 0: The LVD1 circuit is not used. (In standby mode) R/W 1: The LVD1 circuit is used.
PAGE 892
Section 26 Low-Voltage Detection Circuits 26.2.6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Low-Voltage Detection Circuit 0 Control Register H (LD0CRH) Address: H'FF0626 Bit: Value after reset: b7 b6 ⎯ ⎯ ⎯ 0 b5 b4 VD0DFCK[1:0] 0 0 b3 b2 b1 b0 VD0DFS ⎯ ⎯ ⎯ 0 0 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is read as undefined value. The write value should be 0. ⎯ 6 ⎯ Reserved This bit is read as 0.
PAGE 893
Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 26.2.7 Low-Voltage Detection Circuit 0 Control Register L (LD0CRL) Address: H'FF0627 Bit: Value after reset: b7 b6 b5 b4 b3 b2 b1 b0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ VD0LS1 ⎯ 1 0 0 0 0 0 0 1 Bit Symbol Bit Name Description R/W 7 ⎯ Reserved This bit is read as 1. The write value should be 1. ⎯ 6 to 2 ⎯ Reserved This bit is read as 0. The write value should be 0.
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Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 26.3 Operation 26.3.1 Power-On Reset Function Figure 26.5 shows the operation timing of the power-on reset function. During the power-on reset function, the LVD0 circuit monitors the power-supply voltage level to initialize the entire chip. When the power-supply voltage level rises above Vdet0, the prescaler is released from its reset state and it starts counting.
PAGE 895
Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 26.3.2 (1) Low-Voltage Detection Circuit Low Voltage Detect Reset 2 (LVDR2) LVDR2 is a reset generated by the LVD2 circuit. Figure 26.6 shows the operation timing of the LVDR2. The LVD2 enters the module-standby state after release from a power-on reset.
PAGE 896
Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start Set VD2E in LD2CRL to 1. [1] Set VD2E in LD2CRL to activate the LVD2 circuit and wait for the stabilization. [2] Set the digital filter. [1] Wait for td(E-A) period. [3] Set the LVD2 circuit to generate reset requests. [2] Set VD2DFCK[1:0] in LD2CRH. Set VD2DFS in LD2CRH. [3] Set VD2MS in LD2CRH to 1. [4] [4] Enable the LVD2 circuit reset requests. Set VD2RE in LD2CRH to 1.
PAGE 897
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) Section 26 Low-Voltage Detection Circuits Low Voltage Detect Interrupt 2 (LVDI2) LVDI2 is an interrupt generated by the LVD2 circuit. Figure 26.8 shows the operation timing of LVDI2. The LVD2 enters the module-standby state after release from a power-on reset.
PAGE 898
Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group VCC Vdet2 Vdet0 GND LVDINT2 VD2DFS VD2DF VD2UF LVD2 drop interrupt LVD2 rise interrupt Figure 26.8 Operation Timing of LVDI2 Page 872 of 982 REJ09B0465-0300 Rev. 3.
PAGE 899
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 26 Low-Voltage Detection Circuits Start Set VD2E in LD2CRL to 1. [1] Set VD2E in LD2CRL to 1 to activate the LVD2 circuit and wait for the stabilization. [2] Set interrupt request generation conditions when the digital filter is not used. [1] Wait for td(E-A). [2] Set VD2IRCS in LD2CRH. [3] Set the digital filter. [4] Set the LVD2 circuit to generate interrupt requests.
PAGE 900
Section 26 Low-Voltage Detection Circuits (3) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Low Voltage Detect Reset 1 (LVDR1) LVDR1 is a reset generated by the LVD1 circuit. Figure 26.10 shows the operation timing of the LVDR1. The LVD1 enters the module-standby state after release from a power-on reset.
PAGE 901
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 26 Low-Voltage Detection Circuits Start Set VD1E in LD1CRL to 1. [1] [1] Set VD1E in LD1CRL to 1 to activate the LVD1 circuit and wait for the stabilization. [2] Set the digital filter. Wait for td(E-A). [3] Set the LVD1 circuit to generate reset requests. [2] Set VD1DFCK[1:0] in LD1CRH. Set VD1DFS in LD1CRH. [3] Set VD1MS in LD1CRH to 1. [4] [4] Enable the LVD1 circuit reset requests. Set VD1RE in LD1CRH to 1.
PAGE 902
Section 26 Low-Voltage Detection Circuits (4) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Low Voltage Detect Interrupt 1 (LVDI1) LVDI1 is an interrupt generated by the LVD1 circuit. Figure 26.12 shows the operation timing of LVDI1. The LVD1 enters the module-standby state after release from a power-on reset is canceled.
PAGE 903
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 26 Low-Voltage Detection Circuits VCC Vdet1 Vdet0 GND LVDINT1 VD1DFS VD1DF VD1UF LVD1 drop interrupt LVD1 rise interrupt Figure 26.12 Operational Timing of LVDI1 REJ09B0465-0300 Rev. 3.
PAGE 904
Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Start Set VD1E in LD1CRL to 1. [1] Wait for td(E-A). [2] Set VD1IRCS in LD1CRH. [1] Set VD1E in LD1CRL to 1 to activate the LVD1 circuit and wait for the stabilization. [2] Set interrupt request generation conditions when the digital filter is not used. [3] Set the digital filter. [4] Set the LVD1 circuit to generate interrupt requests.
PAGE 905
Section 26 Low-Voltage Detection Circuits H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (5) Low Voltage Detect Reset 0 (LVDR0) LVDR0 is a reset generated by the LVD0 circuit. Figure 26.14 shows the operation timing of the LVDR0. After a power-on reset is released, the LVD0 circuit is always enabled. When the power-supply voltage falls below Vdet0, the LVDR0 clears the LVDRES0 signal to 0, and resets the prescaler, and a power-on reset operation is enabled.
PAGE 906
Section 26 Low-Voltage Detection Circuits Page 880 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300 Rev. 3.
PAGE 907
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 27 List of Registers Section 27 List of Registers The address list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operation mode. The information is given as shown below. 1. • • • • Register Addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified by functional modules.
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Section 27 List of Registers 27.1 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register. Note: Do not attempt to access undefined or reserved addresses. Correct operation of the access itself or later operations is not guaranteed when such an address is accessed.
PAGE 909
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Name Number Abbreviation of Bits Address Module Number of Data Bus Access States Width Port drive control register 5 PDVR5 8 H'FF0034 I/O port 8 2 Port drive control register 6 PDVR6 8 H'FF0035 I/O port 8 2 Port drive control register 8 PDVR8 8 H'FF0037 I/O port 8 2 PDVR9 8 H'FF0038 I/O port 8 2 Port 1 peripheral function mapping PMCR11 register 1 8 H'FF0040 PMC 8
PAGE 910
Section 27 List of Registers Register Name H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Number Abbreviation of Bits Address Module Number of Data Bus Access States Width Port 6 peripheral function mapping PMCR61 register 1 8 H'FF0054 PMC 8 2 Port 6 peripheral function mapping PMCR62 register 2 8 H'FF0055 PMC 8 2 Port 6 peripheral function mapping PMCR63 register 3 8 H'FF0056 PMC 8 2 Port 6 peripheral function mapping PMCR64 register 4 8 H'FF0057 PMC 8 2
PAGE 911
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Name Number Abbreviation of Bits Address Module Number of Data Bus Access States Width Interrupt vector offset register VOFR 16 H'FF0526 Interrupt 8 2 Event link interrupt control status register ELCSR 8 H'FF0528 Interrupt 8 2 Interrupt priority register A IPRA 8 H'FF0529 Interrupt 8 2 Interrupt priority register B IPRB 8 H'FF052A Interrupt 8 2 Interrupt priority reg
PAGE 912
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Name Number Abbreviation of Bits Address Module Number of Data Bus Access States Width Transmit data register_2 TDR_2 8 H'FF055B SCI3_2 8 3 Serial status register_2 SSR_2 8 H'FF055C SCI3_2 8 3 Receive data register_2 RDR_2 8 H'FF055D SCI3_2 8 3 Sampling mode register_2 SPMR_2 8 H'FF055E SCI3_2 8 3 Serial mode register_3 SMR_3 8 H'FF0560 SCI3_3 8 3 Bit rate reg
PAGE 913
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Number Abbreviation of Bits Address Register Name PWM mode output level control 1 register_2* POCR_2 8 H'FF0589 Timer RD digital filtering function 1 select register_2* TRDDF_2 8 H'FF058A TRDCR_3 8 H'FF058B Timer RD I/O control register 1 A_3* TRDIORA_3 8 H'FF058C Timer RD I/O control register 1 C_3* TRDIORC_3 8 Timer RD status register_3* TRDSR_3 Timer RD interrupt enable 1 register_3*
PAGE 914
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Number Abbreviation of Bits Address Module Number of Data Bus Access States Width I C bus mode register ICMR IIC2/SSU 8 2 SS mode register SSMR 8 2 Register Name 2 2 I C bus interrupt enable register ICIER SS enable register SSER 2 I C bus status register ICSR SS status register SSSR Slave address register SAR SS mode register 2 SSMR2 2 I C bus transmit data register ICDRT SS t
PAGE 915
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Number of Data Bus Access States Width Register Name Number Abbreviation of Bits Address Compare voltage register H CMPVALH 8 H'FF05E4 A/D converter (unit 1) 16* 2 A/D data register 3 ADDR3 16 H'FF05E6 A/D converter (unit 1) 16 2 Compare voltage register L CMPVALL 8 H'FF05E6 A/D converter (unit 1) 16* 2 A/D data register 4 ADDR4 16 H'FF05E8 A/D converter (unit 1) 16 2 A/D data
PAGE 916
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Number Abbreviation of Bits Address Register Name Compare control/status 5 register_2* Number of Data Bus Access States Width Module 4 CMPCSR_2 8 H'FF0602 A/D converter (unit 2) 16* 2 ADDR2_2 16 H'FF0604 A/D converter (unit 2) 16 2 CMPVALH_2 8 H'FF0604 A/D converter (unit 2) 16* 2 ADDR3_2 16 H'FF0606 A/D converter (unit 2) 16 2 CMPVALL_2 8 H'FF0606 A/D converter (unit 2) 16*
PAGE 917
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Number Abbreviation of Bits Address Register Name Module Number of Data Bus Access States Width Low-voltage detection circuit control protect register VDCPR 8 H'FF0628 Lowvoltagedetection circuit 8 Timer RG counter TRGCNT 16 H'FF0640 Timer RG 16* General register A GRA General register B 16 H'FF0642 Timer RG 2 3 2 3 2 3 16* GRB 16 H'FF0644 Timer RG 16* 2 Timer RG mode regi
PAGE 918
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Name Number Abbreviation of Bits Address Module Number of Data Bus Access States Width Event link setting register 19 ELSR19 8 H'FF0693 ELC 8 2 Event link setting register 21 ELSR21 8 H'FF0695 ELC 8 2 Event link setting register 22 ELSR22 8 H'FF0696 ELC 8 2 Event link setting register 23 ELSR23 8 H'FF0697 ELC 8 2 Event link setting register 24 ELSR24 8 H'FF0698 E
PAGE 919
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Name Number Abbreviation of Bits Address Module Number of Data Bus Access States Width System clock control register SYSCCR SYSTEM 16* Power-down control register 1 LPCR1 8 8 H'FF06D0 H'FF06D1 SYSTEM 8 2 8 2 8 2 8 2 8 2 8 2 8 16* Power-down control register 2 LPCR2 8 H'FF06D2 SYSTEM 16* Power-down control register 3 LPCR3 8 H'FF06D3 SYSTEM 16* Backup control r
PAGE 920
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Number Abbreviation of Bits Address Module Number of Data Bus Access States Width Timer RC A/D conversion start 6 trigger control register* TRCADCR 8 H'FFFF93 Timer RC 8 2 Timer counter WD TCWD 8 H'FFFF98 WDT 8 2 Timer mode register WD TMWD 8 H'FFFF99 WDT 8 2 Timer control/status register WD TCSRWD 8 H'FFFF9A WDT 8 2 Timer interrupt control register WD TICRWD 8 H'FFFF9B WDT
PAGE 921
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Name Number Abbreviation of Bits Address Timer RD counter_1 TRDCNT_1 16 H'FFFFBA General register A_1 GRA_1 16 H'FFFFBC Module Number of Data Bus Access States Width 3 General register B_1 GRB_1 16 H'FFFFBE 16* Timer RD unit 0 3 16* (channel 1) 3 16* General register C_1 GRC_1 16 H'FFFFC0 16* General register D_1 GRD_1 16 H'FFFFC2 Timer RD control register_0 TRDCR_0 8 H
PAGE 922
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Number Abbreviation of Bits Address Register Name Timer RD output master enable register 1_01 TRDOER1_01 8 H'FFFFD6 Time RD output master enable register 2_01 TRDOER2_01 8 H'FFFFD7 Timer RD output control register_01 TRDOCR_01 8 Timer RC A/D conversion start trigger control register_01 TRDADCR_ 01 Module standby control register 1 Module Number of Data Bus Access States Width 2 H'FFFFD8 8 T
PAGE 923
H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 27 List of Registers 2. Not provided for the H8S/20223 and H8S/20235 Groups. These addresses are reserved. 3. Only 16-bit access is allowed. 4. Access in 8-bit unit. 5. Not provided for the H8S/20103, H8S/20203, H8S/20115, and H8S/20215 Groups. These addresses are reserved. 6. Provided only for the H8S/20103 and H8S/20115 Groups. Addresses for the other groups are reserved. 7.
PAGE 924
Section 27 List of Registers 27.2 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row.
PAGE 925
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PDVR6 PDVR67 PDVR66 PDVR65 PDVR64 PDVR63 PDVR62 PDVR61 PDVR60 I/O Port PDVR87 PDVR86 PDVR85 ⎯ ⎯ ⎯ ⎯ ⎯ PDVR9* PDVR97 PDVR96 PDVR95 PDVR94 PDVR93 PDVR92 PDVR91 PDVR90 PMCR11 ⎯ P11MD[2:0] ⎯ P10MD[2:0]*1 PMCR12 ⎯ P13MD[2:0] ⎯ P12MD[2:0] PMCR13 ⎯ P15MD[2:0] ⎯ P14MD[2:0]*1 PMCR14 ⎯ P1
PAGE 926
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Abbreviation Bit 7 PMCRA4 ⎯ LINCR LINE MST SBE LINST ⎯ ⎯ B2CLR INTCR ⎯ ⎯ IER IRQ7E IRQ6E Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 ⎯ PA7MD[2:0] LSTART B1CLR INTM[1:0] IRQ5E Bit 2 IRQ4E Bit 0 PA6MD[2:0] RXDSF BCIE PMC SBIE SFIE B0CLR BCDCT SBDCT SFDCT NMIEG ADTRG1 ADTRG0 ⎯ IRQ3E IRQ2E IRQ1E IRQ0E ISCRH [IRQ7SCB:IRQ7SCA] [IRQ6SCB:IRQ6SCA] [IRQ5SCB:IRQ5SCA] [IRQ4S
PAGE 927
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 SMR COM CHR PE PM STOP MP CKS[1:0] TIE RIE TE RE MPIE TEIE CKE[1:0] TDRE RDRF OER FER PER TEND MPBR MPBT SPMR ⎯ ⎯ ⎯ ⎯ ⎯ NFEN ⎯ ⎯ SMR_2 COM CHR PE PM STOP MP CKS[1:0] TIE RIE TE RE MPIE TEIE CKE[1:0] TDRE RDRF OER FER PER TEND MPBR MPBT SPMR_2 ⎯ ⎯ ⎯ ⎯ ⎯ NFEN ⎯ ⎯ SMR_3 COM CHR PE
PAGE 928
Section 27 List of Registers Register Abbreviation Bit 7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 5 TRDCNT_3* Module Timer RD Unit 1 (channel 3) GRA_3*5 GRB_3*5 GRC_3*5 GRD_3*5 TRDCR_2*5 CCLR[2:0] ⎯ TRDIORA_2*5 CKEG[1:0] IOB2 IOB[1:0] IOD2 IOD[1:0] TPSC[2:0] ⎯ Timer RD IOA2 IOA[1:0] IOC2 IOC[1:0] Unit 1 (channel 2) 5 TRDIORC_2* IOD3 TRDSR_2*5 5 TRDIER_2* 5 POCR_2* ⎯ ⎯ ⎯ OVF IMFD IMFC IMFB I
PAGE 929
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Abbreviation 5 TRDOER2_23* 5 TRDOCR_23* Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PTO ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Timer RD TOD1 TOC1 TOB1 TOA1 TOD0 TOC0 TOB0 TOA0 ADTRGC1E ADTRGB1E ADTRGA1E ADTRGD0E ADTRGC0E TRDADCR_23*5 ADTRGD1E Unit 1 (channels 2 ADTRGB0E ADTRGA0E and 3 in common) ICCR1 ICE RCVD MST TRS SSCRH ⎯ RSSTP MSS ⎯ ⎯ ICCR2 BBSY SCP SDAO SD
PAGE 930
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module CMPCSR CMPF CMPIE CMPFC1 CMPFC0 ⎯ ⎯ ⎯ ⎯ A/D converter (unit 1) ADDR2 ⎯ CMPVALH ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ VAL9 VAL8 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ VAL5 VAL4 VAL3 VAL2 VAL1 VAL0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ADST ⎯ SCANE SCANS ADM1 ⎯ ⎯ ⎯ ⎯ ⎯ ADDR3 CMPVALL
PAGE 931
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 6 ADDR3_2* A/D ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ VAL3 VAL2 VAL1 VAL0 CMPVALL_2*6 VAL7 VAL6 VAL5 VAL4 ADCSR_2*6 ADIE ADST ⎯ SCANE SCANS ADF ADCR_2*6 TRGS[1:0] ⎯ converter (unit2) *6 CH[2:0] CKS[1:0] ADSTCLR EXTRGS ADMR_2* ⎯ ⎯ ADM1 ⎯ ⎯ ⎯ ⎯ ⎯ RSTFR ⎯ ⎯ SWRST PRST LVD2RST LVD1RST PORRST WRST 6 Module Excep
PAGE 932
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 FLMCR1 ⎯ ⎯ ⎯ ⎯ FMLBD FMWUS FMEWMOD FMCMDEN FLMCR2 ⎯ ⎯ ⎯ FMRDYIE FMBSYRDIE FMISPE FMSPREQ DFPR ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ DFPR1 DFPR0 FLMSTR FMRDYIF FMBSYRDIF FMEBSF FMERSF FMPRSF ⎯ ⎯ FMRDY ELSR0 ELS07 ELS06 ELS05 ELS04 ELS03 ELS02 ELS01 ELS00 ELS17 ELS16 ELS15 ELS14 ELS13 ELS12 ELS11 ELS10 ELSR2* ELS27
PAGE 933
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PGR1 PGR17 PGR16 PGR15 PGR14 PGR13 PGR12 PGR11 PGR10 ELC PGR2 PGR27 PGR26 PGR25 PGR24 PGR23 PGR22 PGR21 PGR20 PGC1 ⎯ PGCO1[2:0] ⎯ PGCOVE1 PGCI1[1:0] PGC2 ⎯ PGCO2[2:0] ⎯ PGCOVE2 PGCI2[1:0] PDBF1 PDBF17 PDBF16 PDBF15 PDBF14 PDBF13 PDBF12 PDBF11 PDBF10 PDBF2 PDBF27 PDBF26 PDBF25 PD
PAGE 934
Section 27 List of Registers Register Abbreviation Bit 7 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TRAPRE Module Timer RA TRATR TRAIR TRAIE TRAIF ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TRCCNT*7 Timer RC GRA*7 GRB*7 GRC*7 GRD*7 TRCMR*7 ⎯ CTS 7 TRCCR1* BUFEB CCLR 7 TRCIER* 7 TRCSR* CKS[2:0] TRCIOR0* PWM2 PWMD PWMC PWMB TOD TOC TOB TOA OVIE ⎯ ⎯ ⎯ IMIED IMIEC IMIEB IMIEA OVF ⎯ ⎯ ⎯ IMFD IMFC IMFB IMFA ⎯ 7
PAGE 935
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Abbreviation Bit 7 Bit 6 TRBIOC ⎯ ⎯ TRBMR TCKCUT Bit 5 Bit 4 TIPF[1:0] TCK[2:0] Bit 3 Bit 2 Bit 1 Bit 0 Module INOSEG INOSTG TOCNT TOPL Timer RB TWRC ⎯ TMOD[1:0] TRBPRE TRBSC TRBPR TRBIR TRBIE TRBIF ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TRESEC BSY SC12 SC11 SC10 SC03 SC02 SC01 SC00 TREMIN BSY MN12 MN11 MN10 MN03 MN02 MN01 MN00 TREHR BSY ⎯ HR11 HR10 HR03 HR02 HR01 HR
PAGE 936
Section 27 List of Registers Register Abbreviation Bit 7 Bit 6 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GRC_1 Module Timer RD Unit 0 (channel 1) GRD_1 TRDCR_0 CCLR[2:0] CKEG[1:0] TPSC[2:0] Timer RD TRDIORA_0 ⎯ IOB2 IOB[1:0] ⎯ IOA2 IOA[1:0] TRDIORC_0 IOD3 IOD2 IOD[1:0] IOC3 IOC2 IOC[1:0] TRDSR_0 ⎯ ⎯ ⎯ OVF IMFD IMFC IMFB IMFA TRDIER_0 ⎯ ⎯ ⎯ OVIE IMIED IMIEC IMIEB IMIEA POCR_0 ⎯ ⎯ ⎯ ⎯ ⎯ PO
PAGE 937
Section 27 List of Registers H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Register Abbreviation MSTCR3 Bit 7 MSTTMRA Bit 6 MSTTMRB Bit 5 Bit 4 3 MSTTMRC* Bit 3 1 MSTTMRD1 MSTTMRD2* 1 Bit 2 Bit 1 Bit 0 Module MSTTMRG ⎯ MSTTMRE 1 PDR1 PDR17 PDR16 PDR15 PDR14* PDR13 PDR12 PDR11 PDR10* PDR2 PDR27 PDR26 PDR25 PDR24 PDR23 PDR22 PDR21 PDR20 PDR3 PDR37 PDR36 PDR35 PDR34 PDR33 PDR32 PDR31 PDR30 PDR5 PDR57 PDR56 PDR55 PDR54 PDR53 PDR52 PDR51
PAGE 938
Section 27 List of Registers Page 912 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300 Rev. 3.
PAGE 939
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Section 28 Electrical Characteristics 28.1 Absolute Maximum Ratings Table 28.1 Absolute Maximum Ratings Item Symbol Value Unit Notes Power supply voltage VCC −0.3 to +6.5 V *1 Analog power supply voltage AVCC −0.3 to +6.5 V All pins VIN (other than AN pin, DA pin, OSC1, and X1) −0.3 to VCC +0.3 V AN pin, DA pin AVIN −0.3 to AVCC +0.3 V OSC1, X1 VIN −0.3 to +1.
PAGE 940
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 28.2 Electrical Characteristics 28.2.1 Power Supply Voltage and Operating Ranges (1) Power Supply Voltage and Oscillation Frequency Range φosc (MHz) φsub (kHz) 20.0 32.768 4.0 2.7 5.5 Vcc(V) 2.7 5.5 VCC (V) φloco (kHz) 125.0 2.7 Page 914 of 982 5.5 VCC (V) REJ09B0465-0300 Rev. 3.
PAGE 941
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group (2) Power Supply Voltage and Operating Frequency Range φ (MHz) 20.0 0.003125 2.7 (3) 5.5 Vcc(V) Accuracy Guarantee Range of Analog Power Supply Voltage and A/D Converter φosc (MHz) 20.0 4.0 2.7 REJ09B0465-0300 Rev. 3.00 Sep 17, 2010 5.
PAGE 942
Section 28 Electrical Characteristics 28.3 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group DC Characteristics Table 28.2 DC Characteristics (1) VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC ≥ AVCC, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), unless otherwise indicated. Values Item Symbol Applicable Pins Input high voltage VIH RES, NMI IRQ0 to IRQ7 Test Condition Typ. Max. Unit Notes VCC = 4.0 to 5.5 V VCC × 0.8 ⎯ VCC + 0.3 V VCC × 0.9 ⎯ VCC + 0.3 V VCC = 4.
PAGE 943
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Values Item Symbol Applicable Pins Input low voltage VIL RES, NMI IRQ0 to IRQ7 Test Condition Min. Typ. Max. Unit VCC = 4.0 to 5.5V −0.3 ⎯ VCC × 0.2 V −0.3 ⎯ VCC × 0.1 V VCC = 4.0 to 5.5V −0.3 ⎯ VCC × 0.3 V −0.3 ⎯ VCC × 0.2 V VCC = 4.0 to 5.5V −0.3 PMRJ[1:0] = 01 ⎯ 0.5 V −0.3 ⎯ 0.
PAGE 944
Section 28 Electrical Characteristics Item Output high voltage H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Setting Condition VOH PDVRn0 to 7 = VCC = 4.0 to VCC −1.0 0 5.5 V −IOH = 5.0mA (n = 1, 2, 3, 5, 6, 8, 9) −IOH = 0.1mA VCC −0.5 P10 to P17 P20 to P27 P30 to P37 P50 to P55 P60 to P67 P85 to P87 P90 to P97 Test Condition Values Applicable Symbol Pins PDVRn0 to 7 = VCC = 4.0 to 1 5.5V (n = 1, 2, 3, 5, 6, 8, 9) Min. ⎯ Typ. Max. Unit Notes ⎯ ⎯ V ⎯ ⎯ V VCC −1.
PAGE 945
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Item Applicable Symbol Pins Output low VOL voltage P10 to P17 P20 to P27 P30 to P37 Setting Condition Test Condition PDVRn0 to 7 = VCC = 4.0 to 0 5.5V (n = 1, 2, 3, 5, 6, 8, 9) Values Min. Typ. Max. Unit Notes ⎯ ⎯ 0.6 V IOL = 1.6mA P50 to P57 IOL = 0.4mA ⎯ ⎯ 0.4 V P60 to P67 PDVRn0 to 7 = VCC = 4.0 to 1 5.5V ⎯ ⎯ 1.5 V IOL = 5.0mA ⎯ ⎯ 1.0 V VCC = 4.0 to 5.5V ⎯ 0.
PAGE 946
Section 28 Electrical Characteristics Item Symbol Input/output leakage current ⎥ IIL ⎥ Applicable Pins NMI, IRQ0 to IRQ7 TRAIO,TRGB, H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Values Test Condition Min. Typ. Max. Unit VIN = 0.5 V to (VCC - 0.5 V) ⎯ ⎯ 1.
PAGE 947
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Item Symbol Applicable Pins Pull-up MOS current −Ip P10 to P17 Values Test Condition Min. Typ. Max. Unit VCC = 5.0 V, VIN = 0.0 V 40.0 ⎯ 200.0 µA VCC = 3.0 V, VIN = 0.0 V ⎯ 40.0 ⎯ µA All input pins except power supply pins f = 1 MHz, VIN = 0.0 V, Ta = 25°C ⎯ ⎯ 15.0 pF VCC Active mode 1, φOSC = 20 MHz ⎯ 20.0 25.0 mA * Active mode 1, φOSC = 10 MHz ⎯ 12.
PAGE 948
Section 28 Electrical Characteristics Item Symbol Sleep mode lSLEEP1 supply current lSLEEP2 lSLEEP3 lSLEEP4 lSLEEP5 Standby mode lSTBY supply current VRAM RAM data retaining voltage Note: * Applicable Pins VCC VCC VCC VCC VCC VCC VCC H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Values Test Condition Min. Typ. Max. Unit Notes Sleep mode 1, φOSC = 20MHz ⎯ 10.0 14.0 mA * Sleep mode 1, φOSC = 10MHz ⎯ 6.
PAGE 949
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Mode RES Pin Internal State Active mode 1 VCC PSCSTP Other Pins Oscillator Pins Operating (φ = φOSC) 0 Active mode 2 Operating (φ = φOSC/64) 0 Active mode 3 Operating (φ = φOSC/128) 0 Only timers operating 0 Sleep mode 2 Only timers operating (φ = φOSC/64) 0 Sleep mode 3 Only timers operating (φ = φOSC/128) 0 Sleep mode 1 Active mode 4 VCC VCC Active mode 5 Sleep mode 4 VCC
PAGE 950
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 28.3 DC Characteristics (2) VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC ≥ AVCC, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), unless otherwise indicated. Item Symbol Allowable output IOL low current (per pin) Applicable Pins Setting Conditions Test Conditions P10 to P17 PDVRn0 to 7 = 0 P20 to P27 (n = 1, 2, 3, 5, 6, 8, 9, J) VCC = 4.0 to 5.
PAGE 951
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Item Symbol Allowable output ⏐ −IOH ⏐ high current (per pin) Applicable Pins Setting Conditions Test Conditions P10 to P17 PDVRn0 to 7 = 0 P20 to P27 (n = 1, 2, 3, 5, 6, 8, 9, J) VCC = 4.0 to 5.5 V P30 to P37 P50 to P55 PDVRn0 to 7 = 1 P60 to P67 (n = 1, 2, 3, 5, 6, 8, 9, J) P85 to P87 VCC = 4.0 to 5.5 V Values Min. Typ. Max. Unit ⎯ ⎯ 5.0 mA ⎯ ⎯ 0.2 mA ⎯ ⎯ 20.
PAGE 952
Section 28 Electrical Characteristics 28.4 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group AC Characteristics Table 28.4 AC Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC ≥ AVCC, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), unless otherwise indicated. Item Applicable Symbol Pins Test Conditions Min. Values Typ. Max. Unit 20.0 MHz Main clock oscillator oscillation frequency φOSC OCS1, OSC2 4.
PAGE 953
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Values Item Test Symbol Applicable Pins Conditions Min. Typ. Max. Unit Reference Figure External clock rise time tCPr OSC1 ⎯ ⎯ 10.0 ns Figure 28.1 External clock fall time tCPf OSC1 ⎯ ⎯ 10.0 ns RES pin low width tREL1 RES 10.0 ⎯ ⎯ ms In active mode 10.
PAGE 954
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Values Item Test Symbol Applicable Pins Conditions Min. Typ. Max. Unit Reference Figure Input pin high width tIH 3 ⎯ ⎯ tcyc Figure 28.4 INCCR[5:4] = 00 300 ⎯ ⎯ ns Figure 28.
PAGE 955
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Item Symbol Test Applicable Pins Conditions Min. Input pin low width tIL FTIOA to FTIOD, 3 Values Typ. Max. Unit Reference Figure ⎯ ⎯ Figure 28.
PAGE 956
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 28.5 Timing of I2C Bus Interface VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC ≥ AVCC, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), unless otherwise indicated. Values Item Symbol Test Conditions Min. Typ. Max.
PAGE 957
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 28.6 Timing of Serial Communication Interface (SCI) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), unless otherwise indicated. Applicable Test Conditions Symbol Pins Item Input clock cycle Asynchronous tscyc SCK3 Clocked synchronous Values Min. Typ. Max. Unit 4 ⎯ ⎯ tcyc 6 ⎯ ⎯ tcyc Input clock pulse width tSCKW SCK3 0.4 ⎯ 0.
PAGE 958
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 28.7 Timing of Synchronous Serial Communication Unit (SSU) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), CL = 100 pF, unless otherwise indicated. Applicable Test Conditions Symbol Pins Item Values Min. Typ. Max. Unit Clock cycle tSUCYC SSCK 4 ⎯ ⎯ tCYC Clock high pulse width tHI SSCK 0.4 ⎯ 0.
PAGE 959
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 28.5 A/D Converter Characteristics Table 28.8 A/D Converter Characteristics VCC = 2.7 to 5.5 V, VSS = AVSS = 0.0 V, VCC ≥ AVCC, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), unless otherwise indicated. Values Applicable Test Conditions Symbol Pins Min. Typ. Max. Unit Notes Analog power supply voltage AVcc AVcc 2.7 Vcc 5.
PAGE 960
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Notes: 1. Set AVcc = Vcc when the A/D converter is not used. 2. AlSTOP1 is the current in active and sleep modes while the A/D converter is idle. 3. AlSTOP2 is the current at reset and in standby, subactive, and subsleep modes while the A/D converter is idle. 28.6 D/A Converter Characteristics Table 28.9 D/A Converter Characteristics VCC = 2.7 to 5.5 V, VSS = AVSS = 0.
PAGE 961
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 28.7 Flash Memory Characteristics Table 28.10 Flash Memory Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC ≥ AVCC, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), unless otherwise indicated. Test Symbol Conditions Target Area Item 1 Values Min. Typ. Max.
PAGE 962
Section 28 Electrical Characteristics Item Read voltage H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Test Symbol Conditions Target Area Values Min. Typ. Max. Unit ⎯ 5.5 V Programmable 1 ROM ⎯ ⎯ tbcyc Data Flash 2 ⎯ ⎯ Programmable 0 ROM ⎯ 60 ⎯ 85 Programmable 2.7 ROM Data Flash Access states Program/erase temperature Data Flash −20* 3 °C Notes: 1.
PAGE 963
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 28.8 Low-Voltage Detection Circuits Characteristics Table 28.11 Electrical Characteristics for Low-Voltage Detection Circuit 0 VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC ≥ AVCC, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), unless otherwise indicated. Values Item Symbol Test Conditions Min. Typ. Max. Unit Voltage-detection level Vdet0 VD0LS1 = 0 2.10 2.35 2.
PAGE 964
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 28.12 Electrical Characteristics for Low-Voltage Detection Circuit 1 VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC ≥ AVCC, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), unless otherwise indicated. Values Item Symbol Test Conditions Min. Typ. Max. Unit Voltage-detection level Vdet1 VD1LS[3:0] = 0111 Falling voltage 2.70 Rising voltage 3.00 3.07 3.30 3.45 3.
PAGE 965
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Table 28.13 Electrical Characteristics for Low-Voltage Detection Circuit 2 VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC ≥ AVCC, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), unless otherwise indicated. Values Item Symbol Test Conditions Min. Typ. Max. Unit Voltage-detection level Vdet2 Falling voltage Rising voltage 3.70 4.00 4.30 V 3.90 4.20 4.50 Vcc = 5.0V ⎯ 2.
PAGE 966
Section 28 Electrical Characteristics 28.9 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Power-On Reset Function Characteristics Table 28.14 Power-On Reset Function Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, VCC ≥ AVCC, Ta = −20 to +85 °C (N version)/ −40 to +85 °C (D version), unless otherwise indicated. Item Symbol Power-on reset valid voltage Vpor External power VCC rise gradient trth Page 940 of 982 Test Conditions Min. Values Typ. Max. Unit 0 ⎯ 0.
PAGE 967
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 28.10 Timing Charts tOSC VIH VIL OSC1 tCPH tCPr tCPL tCPf Figure 28.1 System Clock Input Timing Vcc Vcc×0.7 Low-speed OCO tREL1 RES VIL VIL tREL2 Figure 28.2 RES Pin Low Width Timing REJ09B0465-0300 Rev. 3.
PAGE 968
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group • When switching the clock VCC φosc φbase Oscillation stabilization time trc Switch the clock source to φosc. • When canceling standby mode VCC φosc φbase In standby mode Oscillation stabilization time trc Standby mode canceling trigger Figure 28.3 Oscillation Stabilization Time Timing Page 942 of 982 REJ09B0465-0300 Rev. 3.
PAGE 969
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group NMI, IRQ0 to IRQ7, ADTRG1, ADTRG2, VIH VIL FTIOA to FTIOD, FTIOA0 to FTIOD0, tIL FTIOA1 to FTIOD1, tIH FTIOA2 to FTIOD2, FTIOA3 to FTIOD3, TCLKA, TCLKB, FTCI, TGIOA , TRGC, TGIOB, TRCOI, TRDOI_0, TRDOI_1 Figure 28.
PAGE 970
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group tSCKW SCK3 tscyc Figure 28.6 SCK3 Input Clock Timing tscyc SCK3 VIH or VOH* VIL or VOL* tTXD VOH* VOL* TXD (transmit data) tRXS tRXH RXD (receive data) Note: * Output timing referenced levels Output high VOH = 2.0V Output low VOL = 0.8V Load conditions are shown in figure 28.14. Figure 28.7 SCI Input/Output Timing in Clocked Synchronous Mode Page 944 of 982 REJ09B0465-0300 Rev. 3.
PAGE 971
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group tHI VIH or VOH SSCK VIL or VOL tLO tSUCYC SSO (Output) tOD SSI (Input) tSU tH Figure 28.8 SSU Input Timing in Clocked Synchronous Communication Mode SCS (Output) VIH or VOH VIL or VOL tFALL tHI tRISE SSCK (Output) CPOS = 1 tLO tHI SSCK (Output) CPOS = 0 tLO tSUCYC SSO (Output) tOD SSI (Input) tSU tH Figure 28.
PAGE 972
Section 28 Electrical Characteristics SCS (Output) H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group VIH or VOH VIL or VOL tFALL tHI tRISE SSCK (Output) CPOS = 1 tLO tHI SSCK (Output) CPOS = 0 tLO tSUCYC SSO (Output) tOD SSI (Input) tSU tH Figure 28.10 SSU Input/Output Timing (Four-Line Bus Communication Mode, Master, CPHS = 0) Page 946 of 982 REJ09B0465-0300 Rev. 3.
PAGE 973
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group SCS (Input) VIH or VOH VIL or VOL tLEAD tFALL tHI tRISE tLAG SSCK (Input) CPOS = 1 tLO tHI SSCK (Input) CPOS = 0 tLO tSUCYC SSO (Input) tSU tH SSI (Output) tSA tOD tOR Figure 28.11 SSU Input/Output Timing (Four-Line Bus Communication Mode, Slave, CPHS = 1) REJ09B0465-0300 Rev. 3.
PAGE 974
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group VIH or VOH SCS (Input) VILor VOL tLEAD tFALL tHI tRISE tLAG SSCK (Input) CPOS = 1 tLO tHI SSCK (Input) CPOS = 0 tSUCYC tLO SSO (Input) tSU tH SSI (Output) tOD tSA tOD Figure 28.
PAGE 975
Section 28 Electrical Characteristics H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group 28.11 Output Load Circuit Vcc 2.4kΩ LSI output pin 30pF 12kΩ Figure 28.14 Output Load Circuit REJ09B0465-0300 Rev. 3.
PAGE 976
Section 28 Electrical Characteristics Page 950 of 982 H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300 Rev. 3.
PAGE 977
Appendix H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Appendix A. Package Dimensions JEITA Package Code P-LQFP64-10x10-0.50 RENESAS Code PLQP0064KB-A Previous Code 64P6Q-A / FP-64K / FP-64KV MASS[Typ.] 0.3g HD *1 D 48 33 49 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
PAGE 978
Appendix H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group JEITA Package Code P-LQFP64-14x14-0.80 RENESAS Code PLQP0064GA-A Previous Code 64P6U-A MASS[Typ.] 0.7g HD *1 D 33 48 49 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
PAGE 979
Appendix H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group JEITA Package Code P-LQFP80-14x14-0.65 RENESAS Code PLQP0080JA-A Previous Code FP-80W / FP-80WV MASS[Typ.] 0.6g HD *1 D 41 60 61 40 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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Appendix B. H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group Handling of Unused Pins Table B.1 shows the handling of unused pins. Table B.1 Handling of Unused Pins Pin Name Example of Handling Pins RES Connect this pin to VCC via a pull-up resister NMI Connect this pin to VCC via a pull-up resister X1 Connect this pin to VSS X2 Leave this pin open Port 1 Set the corresponding PMR bit or the PCR bit to 0 to set these pins in general purpose mode.
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Main Revisions and Additions in this Edition Changes in Rev. 3.00 Compared to Rev. 2.00 Item Page Revision (See Manual for Details) Section 1 Overview 1 Amended 1.1 Features 1.1.2 Overview of Functions Table 1.1 Overview of Functions REJ09B0465-0300 Rev. 3.
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Item Page Revision (See Manual for Details) 1.4 Pin Assignments 19 Amended 1.4.1 Pin Functions Pin No. Table 1.
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Item Page Revision (See Manual for Details) Section 4 Interrupt Controller 78 Deleted 4.2 Register Descriptions Bit Description 4.2.1 Interrupt Control Register (INTCR) 2 0: AD1 or AD2 conversion is started at falling edge of ADTRG2 input. 1: AD1 or AD2 conversion is started at rising edge of ADTRG2 input. 4.2.5 IRQ Status Register (ISR) 85 Description amended 4.2.
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Item Page Revision (See Manual for Details) 7.4 Register Descriptions 164 Amended 7.4.2 Flash Memory Control Register 2 (FLMCR2) Notes: 1. For programming the flash memory, set the FMSPEN bit to 1. 2. The FMRDYIE bit is cleared to 0 when the FMCMDEN bit changes from 0 to 1. 3. The FMBSYRDIE bit is cleared to 0 when the FMCMDEN bit changes from 0 to 1. 7.6 Programming/Erasing 215 7.6.
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Item Page Revision (See Manual for Details) Section 9 Peripheral I/O Mapping Controller 237 Amended Table 9.1 Multiplexed Pin Functions (Ports 1, 2, 3, 5, and 6) Group 1 Pin Name Function 4 Port 1 Pm7 SCL/SSI input/output Pm6 SDA/SCS input/output Port 2 Port 3 Port 5 Port 6 Notes: 1. The timer RC is not available on the H8S/20203, H8S/20223, H8S/20215, and H8S/20235 Groups; therefore, the function cannot be selected for these groups. 2.
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Item Page (d) Port 1 Peripheral Function 244 Mapping Register 4 (PMCR14) (d) Port 2 Peripheral Function 248 Mapping Register 4 (PMCR24) Revision (See Manual for Details) Amended Bit Description 6 to 4 : 1 100: SSI/SCL input/output* (SSU/IIC2) 101: FTIOD1 input/output (timer RD_0) 110: ADTRG2 input (AD_2) 111: Setting prohibited 2 to 0 : 1 2 100: SCS/SDA input/output* * (SSU/IIC2) 101: FTIOC1 input/output (timer RD_0) 110: ADTRG1 input (AD_1) 111: Setting prohibited Notes: 1.
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Item Page (d) Port 3 Peripheral Function 252 Mapping Register 4 (PMCR34) Revision (See Manual for Details) Amended Bit Description 6 to 4 : 1 100: SSI/SCL input/output* (SSU/IIC2) 101: FTIOD1 input/output (timer RD_0) 110: ADTRG2 input (AD_2)*1 111: Setting prohibited 2 to 0 : 100: SCS/SDA input/output*1*2 (SSU/IIC2) 101: FTIOC1 input/output (timer RD_0) 110: ADTRG1 input (AD_1) 111: Setting prohibited Notes: 1.
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Item Page (d) Port 6 Peripheral Function 261 Mapping Register 4 (PMCR64) Revision (See Manual for Details) Amended Bit Description 6 to 4 : 1 100: SSI/SCL input/output* (SSU/IIC2) 101: FTIOD1 input/output (timer RD_0) (initial value) 110: ADTRG2 input (AD_2) *1 111: Setting prohibited 2 to 0 : 100: SCS/SDA input/output*1*2 (SSU/IIC2) 101: FTIOC1 input/output (timer RD_0) (initial value) 110: ADTRG1 input (AD_1) 111: Setting prohibited Notes: 1.
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Item Page 10.8.11 Port Data Register A 324 (PDRA) Revision (See Manual for Details) Amended PDRA is a register that stores output data for port A pins. When PCRA bits are set to 1, the values stored in PDRA are output. … When the pins are set as analog input channels by ADCSR and ADCR of the A/D converter, however, the corresponding PDRA bits are always read as 1 even if the respective PCRA bits are cleared to 0. 10.
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Item Page Revision (See Manual for Details) 11.8 Usage Notes 368 Added 370 Amended 11.8.4 Limitation on Usage of the Interrupt Vector Offset Register (VOFR) Section 12 Event Link Controller 12.1 Overview Figure 12.1 Block Diagram of Event Link Controller ELCR ELSR0 to ELSR32 12.2 Register Descriptions 372 Amended 12.2.2 Event Link Setting Registers 0 to 32 (ELSR0 to ELSR32) … Table 12.1 shows the correspondence between ELSR0 to ELSR32 and the peripheral modules. … 12.2.
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Item Page Revision (See Manual for Details) Section 14 Timer RB 421 Amended 14.2 Register Descriptions Bit Symbol Description 14.2.1 Timer RB Control Register (TRBCR) 1 TCSTF : [Setting conditions] • • When 1 is written to TSTART and counting is started. The start of counting after ELOPA of the event link controller is selected counting by timer RB, the specified event is occurred, and the TSTART bit is set to 1. : 14.2.5 Timer RB Interrupt Request Status Register (TRBIR) 426 14.
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Item Page Revision (See Manual for Details) Section 15 Timer RC 462 Amended 15.2 Register Descriptions … If the corresponding interrupt-enable bit (the IMIEA, IMIEB, IMIEC, or IMIED bit) in TRCIER is set to 1 at this time, an interrupt request is generated. … 15.2.12 General Registers A, B, C, and D (GRA, GRB, GRC, and GRD) 15.3 Operation 481 Input signals on the FTIOA to FTIOD and TRGC pin can be input via the digital filters.
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Item Page Revision (See Manual for Details) Section 16 Timer RD 526 Deleted 16.2 Register Descriptions Notes: 1. When a GR register functions as a buffer register for a paired GR register, the settings in the IOA2 and IOB2 bits in TRDIORA and the IOC2 and IOD2 bits in TRDIORC of both registers should be the same. The IOA3 bit exists only in TRDIORA_0. 16.2.12 Timer RD I/O Control Registers (TRDIORA and TRDIORC) 2.
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Item Page Revision (See Manual for Details) 16.3.11 Digital Filtering Function for Input Capture Inputs 588 Deleted TPSC1 to TPSC0 Figure 16.54 Block Diagram of Digital Filter φ/32 φ/8 φ FTIOA0 (TCLK) φ40 φ/32 φ/8 φ/4 φ/2 φ C FTIOA to FTIOD C Q D Latch D Q Latch φ, φ40M C D Q Latch 16.3.14 Operation by Event Clear 593 The counting of events by timer RD can be selected by ELOPA and ELOPB of the ELC.
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Item Page Revision (See Manual for Details) 17.4 Operation of Output Compare Mode 623 Amended Section 18 Timer RG 643, 644 Tables amended 645 Replaced Figure 18.8 Input Capture Input Signal Timing 650 Replaced 18.3.2 PWM Mode 651 Replaced 18.3.3 Phase Counting Mode 660 Amended Figure 18.17 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Pulse width: 3 states or more 18.3 Operation • TGIOA pin • TGIOB pin 18.3.
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Item Page Revision (See Manual for Details) 18.3.5 Operation through an Event Link 663 Added … When the event specified in ELSR8 occurs, event counter operation proceeds with that event as the source to drive counting, regardless of the setting of TPSC[2:0] bits in TRGCR and the STR bit in TRGMDR. … (2) Counting Event 18.3.6 Digital Filtering Function for Input Capture Inputs 664 Deleted TPSC2 to TPSC0 φ/32 φ/8 φ TCLKB TCLKA Figure 18.
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Item Page Revision (See Manual for Details) 20.2 Register Descriptions 682 Amended Channel 2 • Receive shift register_2 (RSR_2) • Receive data register_2 (RDR_2) • Transmit shift register_2 (TSR_2) • Transmit data register_2 (TDR_2) • Serial mode register_2 (SMR_2) • Serial control register_2 (SCR3_2) • Serial status register_2 (SSR_2) • Bit rate register_2 (BRR_2) • Sampling mode register_2 (SPMR_2) • IrDA control register_2 (IrCR_2) Channel 3 20.6.
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Item Page Revision (See Manual for Details) 20.8 Interrupt Requests 724 Amended … When the RDRF flag in SSR is set to 1, a RXI interrupt request is generated. When any of the OER, PER and FER flags is set to 1, an ERI interrupt request is generated. The DTC can be activated to perform data transfers with the RXI interrupt request. The RDRF flag is automatically cleared to 0 by the DTC data transfer. 20.9 Usage Notes 727 Amended 20.9.6 Restrictions on Using DTC [Before amendment] Figure 20.
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Item 21.2 Register Descriptions 2 21.2.3 I C Bus Control Register 2 (ICCR2) Page Revision (See Manual for Details) 735, 736 Added Bit Symbol 1 3 7 BBSY* * 6 SCP* 5 SDAO* 3 Description 2 This bit enables to confirm whether the I C bus is… The SCP bit controls the issue of start/stop… 3 This bit is used with SDAOP (bit 4) when modifying output level of SDA. This bit should not be manipulated during transfer. Writing 1 to the IICRST bit also sets this bit to 1.
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Item Page 21.6.4 Note on Access to ICE 766 in ICCR1 and IICRST in ICCR2 during I2C Bus Operation Section 22 Synchronous Serial Communication Unit (SSU) 780 Revision (See Manual for Details) Added Added … If the MLS bit in SSMR is set to 1 and when the data is written to SSTDR, the MSB/LSB inverted data is read. SSTDR is initialized to H'FF. In standby mode, SSTDR is initialized. 22.2 Register Descriptions 22.2.9 SS Transmit Data Register (SSTDR) 22.2.10 SS Shift Register (SSTRSR) 780 22.
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Item Page Revision (See Manual for Details) Section 23 Hardware LIN 811 Deleted 23.3 Operation The hardware LIN interface can detect bus conflicts if SCI3_1 is enabled for transmission (TE bit in SCR3_1 register is 1). 23.3.3 Bus Conflict Detection Function Section 24 A/D Converter 817 Added 24.1 Features AN0_2 AN1_2 AN2_2 AN3_2 Multiplexer + Figure 24.
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Item Page Revision (See Manual for Details) 24.5 Compare Mode Operation 841 Amended A/D conversion can be externally triggered. When the EXTRGS, TRGS1, and TRGS0 bits are set to B'001 in ADCR, external trigger input is enabled at the ADTRG pin. 24.5.4 External Trigger Input Timing Section 26 Low-Voltage Detection Circuits 859 26.2 Register Descriptions Amended Bit Symbol R/W 7 WRI W 26.2.1 Low-Voltage Detection Circuit Control Protect Register (VDCPR) 26.3 Operation 868 Amended 26.3.
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Item Page Revision (See Manual for Details) Section 27 List of Registers 885, 886 Amended 27.
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Item Page Revision (See Manual for Details) 27.1 Register Addresses (Address Order) 897 Note added Notes: 1. … 2. Not provided for the H8S/20223 and H8S/20235 Groups. These addresses are reserved. 27.2 Register Bits Page 978 of 982 — Amended REJ09B0465-0300 Rev. 3.
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Index A A/D conversion time............................... 839 A/D Converter ........................................ 815 Absolute Address...................................... 56 Acknowledge .......................................... 747 Activation by Software ................... 359, 363 Addressing Mode...................................... 55 ADI ......................................................... 842 Advanced Mode........................................ 24 Arithmetic Operations Instructions.....
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M Memory Indirect....................................... 58 N NMI ........................................................ 106 NMI Interrupt ........................................... 89 Noise canceler ........................................ 758 Normal Mode.......................................... 355 O Operation Field......................................... 53 P Pin functions............................................. 14 Program Counter ......................................
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OSCCSR............................................. 121 PCR.............273, 279, 285, 291, 297, 303, .....................309, 315, 319, 323, 327, 332 PDR ....................274, 280, 286, 292, 298, .............................304, 310, 316, 324, 333 PMR....................272, 278, 284, 290, 296, .....................302, 308, 314, 318, 322, 331 POCR.................................................. 533 RDR.................................................... 683 RSR......................................
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TRAPA..................................................... 57 TRAPA instruction ................................... 72 W Waveform output by compare match...... 548 V Vector number for the software activation interrupt.................................. 345 Page 982 of 982 REJ09B0465-0300 Rev. 3.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group User’s Manual: Hardware Publication Date: Rev.1.00 Rev.3.
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http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.
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H8S/20103, H8S/20203, H8S/20223, H8S/20115, H8S/20215, H8S/20235 Group REJ09B0465-0300