Instruction manual

Renesas USB MCU and USB ASSP USB Basic Host and Peripheral firmware
R01AN0512EJ0210 Rev.2.10 Page 151 of 157
Apr 1, 2013
11. DTC/EXDMA Transfer
11.1 Overview
In RX62N, RX63N, RX63T and RX630, when D0FIFO access (USBC_D0DMA) is specified in the pipe information
table, USB-BASIC-FW uses the DTC for FIFO access. In RX6N + R8A6667, FIFO access between SDRAM on
RX62N-RSK and R8A66597 is used EXDMA. Note that the DTC/EXDMA is a system-dependent function, so the
settings for transfer method, access timing, communication start/end timing, DTC/EXDMA, etc., should be changed as
necessary to match the system under development.
Please refer to EXDMA transfer block diagram (
Figure 11-1) when using R8A66597/R8A66593.
11.1.1 Basic Specification
The specifications of the DTC transfer sample program code included in USB-BASIC-FW are listed below. DTC settings
are made by the usb_cpu_d0fifo2buf_start_dma (),usb_cpu_buf2d0fifo_start_dma () function in the rx_rsk.c file. When
DTC is specified in the pipe information table, the usb_cstd_SendStart() or usb_cstd_ReceiveStart() function makes DTC
transfer settings.
Modify the DTC/EXDMA control sample functions usb_cpu_d0fifo2buf_start_dma () and
usb_cpu_buf2d0fifo_start_dma () and the DTC/EXDMA settings as necessary to match the system under development.
And, pipe 1 to pipe5 can used DTC/EXDMA access.
Table 11-1 shows DTC Setting Specifications.
Table 11-1 DTC Setting Specifications
Setting Description
FIFO port used D0FIFO port
Transfer mode Block transfer mode
One DTC transfer size: max packet size.
Chain transfer Disabled
Address mode Full address mode
Read skip Disabled
Access bit width (MBW) 2-byte transfer: 16-bit width
1-byte transfer: 8-bit width
(In data reception (D0FIFO to RAM), this setting is 16-bit width.)
Transfer end Receive direction: BRDY interrupt
Transmit direction: BEMP interrupt
Table11-2 EXDMA Setting Specifications
Setting Description
FIFO port used D0FIFO port
Transfer mode Block transfer mode
One EXDMAC transfer size :
Max Packe Size of the transfer PIPE
Address mode Single Address mode
(This is that R8A66597/R8A66593 is accessed by the EDACKn
signal and transfer the data by specifing the address to SDRAM.)
R8A66597/R8A66593
Control signal
Port 5 bit 5(P55)：EDREQ0-C pin
Port 5 bit 4(P54)：EDACK0-C pin
Access bit width (MBW) 2-byte transfer: 16-bit width
Transfer end Receive direction: BRDY interrupt
Transmit direction: BEMP interrupt