Instruction manual

Renesas USB MCU and USB ASSP USB Basic Host and Peripheral firmware
R01AN0512EJ0210 Rev.2.10 Page 118 of 157
Apr 1, 2013
Additional Communication Structure details for host
1. Buffer address for USB communication (tranadr)
Reception or ControlRead transfer: Specifies the address of the buffer for storing receive data.
Transmission or ControlWrite transfer: Specifies the address of the buffer for storing transmit data.
NoDataControl transfer: Ignored if specified.
2. USB communication data length (tranlen)
Reception or ControlRead transfer: Stores the receive data length.
Transmission or ControlWrite transfer: Stores the transmit data length.
NoDataControl transfer: Set to 0.
The remaining transmit/receive data length is stored after USB communication end. In case of control transfer in host
mode, the remaining data length from the data stage is stored.
3. Setup packet data (setup)
For control transfers using R_usb_hstd_TransferStart(), the structure member (*setup) is a USB request data table stored
in the hardware registers listed below.
For *setup, specify the table address of the uint16_t[5] array.
Table 5.11 setup_packet array
Register Name Value
54H USBREQ bRequest bmRequestType
56H USBVAL wValue
58H USBINDX wIndex
5AH USBLENG wLength
-- USBADDR Device Address
4. Pipe control (pipectr)
An HDCD driver can communicate with multiple endpoint addresses over a single pipe by remembering the sequence
toggle bit. When specifying transfer continuation, set the SQMON bit in this register to the previous toggle state.
5. Segment information (pipectr)
Control transfer continuation: Specify USBC_TRAN_CONT (continuation of transfer from data stage enabled).
Control transfer end: Specify USBC_TRAN_END.
Data transfer continuation: Specify USBC_TRAN_CONT. (Set SQMON bit in PIPECTR.)
Data transfer end: Specify USBC_TRAN_END. During isochronous transfer no determination is made
when pipe is in use.
5.8.5 Notes on Data Transfer
When the maximum packet size is an odd number and one packet is not equivalent to one transfer, the CPU may generate
an address exception during buffer access.