Technical information

Section 3 Software Specifications when Using the SH7080 Series/SH7146 Series/SH/Tiny Series
Rev. 5.00 Aug. 18, 2009 Page 44 of 78
REJ10J1237-0500
Set the address condition as H’2000 in the [Event Condition 4] dialog box.
Set [Ch4, 5] as [I-Trace Ch5 to Ch4 PtoP] in the [Combination action] dialog box.
When point-to-point and trace acquisition condition are set simultaneously, they are ANDed.
Notes on Internal Trace:
• Timestamp
The timestamp is twice the crystal oscillator or the external clock that is connected to or input
to the target MCU. Table 3.13 shows the timing for acquiring the timestamp.
Table 3.13 Timing for the Timestamp Acquisition
Item Counter Value Stored in the Trace Memory
L-bus instruction fetch Counter value when instruction fetch has been
completed
L-bus data access Counter value when data access has been completed
Branch Counter value when the next bus cycle has been
completed after a branch
I-bus fetch Counter value when a fetch has been completed
I-bus data access Counter value when data access has been completed
• Point-to-point
The trace-start condition is satisfied when the specified instruction has been fetched.
Accordingly, if the trace-start condition has been set for the overrun-fetched instruction (an
instruction that is not executed although it has been fetched at a branch or transition to an
interrupt), tracing is started during overrun-fetching of the instruction. However, when
overrun-fetching is achieved (a branch is completed), tracing is automatically suspended.
If the start and end conditions are satisfied closely, trace information will not be acquired
correctly.
The execution cycle of the instruction fetched before the start condition is satisfied may be
traced.
• Halting a trace
Do not set the trace end condition for the sleep instruction and the branch instruction that the
delay slot becomes the sleep instruction.