Technical information

Section 3 Software Specifications when Using the SH7080 Series/SH7146 Series/SH/Tiny Series
Rev. 5.00 Aug. 18, 2009 Page 39 of 78
REJ10J1237-0500
Notes: 1. If the Event condition is set for the slot in the delayed branch instruction by the
program counter (after execution of the instruction), the condition is satisfied before
executing the instruction in the branch destination (when a break has been set, it occurs
before executing the instruction in the branch destination).
2. Do not set the Event condition for the SLEEP instruction by the program counter (after
execution of the instruction).
Do not set the Event condition by an operand access before executing two instructions
in the SLEEP instruction.
3. If the power-on reset and the Event condition are matched simultaneously, no condition
will be satisfied.
4. If a condition of which intervals are satisfied closely is set, no sequential condition will
be satisfied. Set the Event conditions sequentially, which are satisfied closely, by the
program counter with intervals of two or more instructions. If a power-on reset is
generated immediately before a break occurs when a sequential condition is matched,
the halt condition will not be displayed correctly.
The CPU is structured as a pipeline; the order between the instruction fetch cycle and
the memory cycle is determined by the pipeline. Accordingly, when the channel
condition is matched in the order of bys cycle, the sequential condition is satisfied.
5. If the settings of the Event condition or the sequential conditions are changed during
execution of the program, execution will be suspended. (The number of clocks to be
suspended during execution of the program is a maximum of about 52 bus clocks (Bφ).
If the bus clock (Bφ) is 10.0 MHz, the program will be suspended for 5.2 μs.)
6. If the settings of Event conditions or the sequential conditions are changed during
execution of the program, the emulator temporarily disables all Event conditions to
change the settings. During this period, no Event condition will be satisfied.
7. If the satisfaction is contended between the DMA or DTC transfer and conditions of
Event Condition including the external bus access condition, the followings may be
disabled: generation of a break after the satisfaction of conditions of Event Condition,
halting and acquisition of the internal trace, and the start or end of performance
measurement.
8. When the emulator is being connected, the user break controller (UBC) function is not
available.