User`s manual
81
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
MITSUBISHI MICROCOMPUTERS
Rev. 1.0
M37281MAH–XXXSP,M37281MFH–XXXSP
M37281MKH–XXXSP,M37281EKSP
8.11.5 Field Determination Display
To display the block with vertical dot size of 1/2H, whether an even
field or an odd field is determined through differences in a synchro-
nizing signal waveform of interlacing system. The dot line 0 or 1 (re-
fer to Figure 8.11.19) corresponding to the field is displayed alter-
nately.
In the following, the field determination standard for the case where
both the horizontal sync signal and the vertical sync signal are nega-
tive-polarity inputs will be explained. A field determination is deter-
mined by detecting the time from a falling edge of the horizontal sync
signal until a falling edge of the VSYNC control signal (refer to Figure
Fig. 8.11.18 I/O Polarity Control Register
8.11.9) in the microcomputer and then comparing this time with the
time of the previous field. When the time is longer than the compar-
ing time, it is regarded as even field. When the time is shorter, it is
regarded as odd field.
The field determination flag changes at a rising edge of VSYNC con-
trol signal in the microcomputer.
The contents of this field can be read out by the field determination
flag (bit 7 of the I/O polarity control register at address 021716). A dot
line is specified by bit 6 of the I/O polarity control register (refer to
Figure 8.11.19).
However, the field determination flag read out from the CPU is fixed
to “0” at even field or “1” at odd field, regardless of bit 6.
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
I
/
O
p
o
l
a
r
i
t
y
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
P
C
)
[
A
d
d
r
e
s
s
0
2
1
7
1
6
]
B
N
a
m
e
F
unct
i
on
s
A
f
t
e
r
r
e
s
e
t
R
W
I
/
O
P
o
l
a
r
i
t
y
C
o
n
t
r
o
l
R
e
g
i
s
t
e
r
0
H
SYNC
i
nput po
l
ar
i
ty
switch bit (PC0)
0 :
P
os
i
t
i
ve po
l
ar
i
ty
i
nput
1 : Negative polarity input
0
10 :
P
os
i
t
i
ve po
l
ar
i
ty
i
nput
1 : Negative polarity input
0
2
R
,
G
,
B
output po
l
ar
i
ty
switch bit (PC2)
0 :
P
os
i
t
i
ve po
l
ar
i
ty output
1 : Negative polarity output
0
3 0
V
S
Y
N
C
i
n
p
u
t
p
o
l
a
r
i
t
y
s
w
i
t
c
h
b
i
t
(
P
C
1
)
R
W
R
W
R
W
R
—
N
ote:
R
e
f
er to
Fi
g. 8.11.19.
0 : “ ” at even
fi
e
ld
“ ” at odd field
1 : “ ” at even field
“ ” at odd field
4
O
U
T
1
o
u
t
p
u
t
p
o
l
a
r
i
t
y
s
w
i
t
c
h
b
i
t
(
P
C
4
)
0 :
P
os
i
t
i
ve po
l
ar
i
ty output
1 : Negative polarity output
0
5
O
U
T
2
o
u
t
p
u
t
p
o
l
a
r
i
t
y
s
w
i
t
c
h
b
i
t
(
P
C
5
)
0 :
P
os
i
t
i
ve po
l
ar
i
ty output
1 : Negative polarity output
0
6
D
i
s
p
l
a
y
d
o
t
l
i
n
e
s
e
l
e
c
t
i
o
n
b
i
t
(
P
C
6
)
(
S
e
e
n
o
t
e
)
0
7
Fi
e
ld
d
eterm
i
nat
i
on
flag(PC7)
0 :
E
ven
fi
e
ld
1 : Odd field
1
R
W
R
W
R
W
R
—
N
ot
hi
ng
i
s ass
i
gne
d
.
Thi
s
bi
t
i
s a wr
i
te
di
sa
bl
e
bi
t.
When this bit is read out, the value is “0”.